Electrical computers and digital processing systems: memory – Address formation – Generating a particular pattern/sequence of addresses
Reexamination Certificate
2001-08-14
2004-06-01
Padmanabhan, Mano (Department: 2188)
Electrical computers and digital processing systems: memory
Address formation
Generating a particular pattern/sequence of addresses
C711S217000, C711S218000, C712S204000
Reexamination Certificate
active
06745315
ABSTRACT:
TECHNICAL FIELD
The invention in one embodiment relates generally to communications and more particularly to information and signal processing.
BACKGROUND
Parallel processors are useful for many types of communications and multimedia signal processing. One challenge in working with one example of a parallel processing engine is keeping the parallel processing engine supplied with data. A failure to keep the parallel processing engine supplied with data disadvantageously prevents a realization of a number of benefits of parallel processing, such as a linear processing speedup.
A parallel processor comprises a number of processing elements, for instance, multipliers, adders, and the like. However, unless these processing elements are provided with the data at a correct time, these processing elements will disadvantageously go unused, for example, greatly reducing processing efficiency.
To obtain increased (e.g., maximum) processing speedup for a parallel computation, a single instruction-stream, multiple data-stream (“SIMD”) processor in one example needs to access data samples in a single read cycle from memory. Non-unit strides through memory that serve to access non-adjacent data samples in specific patterns in one example present problems for management of the data upon reading. Exemplary communications system signal processing tasks that employ non-unit strides through memory in specific patterns include oversampled synchronization (“sync”) correlation, fast Fourier transforms (“FFTs”), interpolation processes, and decimation processes.
Thus, a need exists for enhanced storage of information that is employed in multiprocessing. A further need exists for enhanced access to information that is employed in multiprocessing.
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Desai Vipul Anil
Gurney David P.
Haas Kenneth A.
Motorola Inc.
Namazi Mehdi
Padmanabhan Mano
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