Generating isolated bus cycles for isolated execution

Details Generating isolated bus cycles for isolated execution Generating isolated bus cycles for isolated execution

2006-09-19

2006-09-19

Jung, David (Department: 2134)

Electrical computers and digital processing systems: support

Multiple computer communication using cryptography

Protection at a particular protocol layer

C713S189000, C713S190000

Reexamination Certificate

active

07111176

ABSTRACT:
The present invention is a method and apparatus to generates an isolated bus cycle for a transaction in a processor. A configuration storage contains configuration parameters to configure a processor in one of a normal execution mode and an isolated execution mode. An access generator circuit generates an isolated access signal using at least one of the isolated area parameters and access information in the transaction. The isolated access signal is asserted when the processor is configured in the isolated execution mode. A bus cycle decoder generates an isolated bus cycle corresponding to a destination in the transaction using the asserted isolated access signal and the access information.

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