Electrical computers and digital processing systems: memory – Address formation – Generating prefetch – look-ahead – jump – or predictive address
Reexamination Certificate
2005-06-13
2008-09-30
Ellis, Kevin (Department: 2187)
Electrical computers and digital processing systems: memory
Address formation
Generating prefetch, look-ahead, jump, or predictive address
C711S137000, C712S207000
Reexamination Certificate
active
07430650
ABSTRACT:
Cache prefetching algorithm uses previously requested address and data patterns to predict future data needs and prefetch such data from memory into cache. A requested address is compared to previously requested addresses and returned data to compute a set of increments, and the set of increments is added to the currently requested address and returned data to generate a set of prefetch candidates. Weight functions are used to prioritize prefetch candidates. The prefetching method requires no changes to application code or operation system (OS) and is transparent to the compiler and the processor. The prefetching method comprises a parallel algorithm well-suited to implementation on an application-specific integrated circuit (ASIC) or field-programmable gate array (FPGA), or to integration into a processor.
REFERENCES:
patent: 6173392 (2001-01-01), Shinozaki
patent: 6311260 (2001-10-01), Stone et al.
patent: 6636945 (2003-10-01), Nakamura
patent: 6976147 (2005-12-01), Isaac et al.
Ellis Kevin
Fernandez & Associates LLP
Parikh Kalpit
Ross Richard
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