Generating a 2-phase clock using a non-50% divider circuit

Details Generating a 2-phase clock using a non-50% divider circuit Generating a 2-phase clock using a non-50% divider circuit

2000-05-22

2003-09-30

Lee, Thomas (Department: 2185)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C713S401000, C713S503000, C327S100000

Reexamination Certificate

active

06629255

ABSTRACT:

FIELD OF THE INVENTION
This invention is generally related to digital clock circuits, and more particularly to techniques for generating a 2-phase clock.
BACKGROUND
Conventional clock circuits generate periodic digital signals, for instance those having a square wave with a 50% duty cycle, for timing purposes in various applications. Certain applications, such as microprocessor and computer bus timing, require a so-called “2-phase clock” that has two separate output signals. One of these signals asserts a pulse responsive to a rising edge of an input clock whereas the other asserts a pulse responsive to the falling edge of the input clock. These output signals are usually generated locally, i.e. physically near the logic functional units which are clocked by them, using latches and flip-flops that are fed by a single input clock which is distributed over the integrated circuit (IC) die or printed wiring board (PWB). In most cases, these latches and/or flip flops are required to have the same time delay in generating their respective pulses. Such a requirement may be defined as D
1
=D
2
as shown in the timing diagram of FIG.
1
.
A technique to generate the 2-phase clock shown in
FIG. 1
is depicted in
FIG. 2. A
divider circuit
204
divides a double frequency clock derived from a phase locked loop (PLL) by two, resulting in a 50% duty cycle input clock. The output of the divider circuit
204
is distributed and fed to a local digital delay circuit
208
having two paths. One path has an even number of inverter elements whereas the other has an odd number, to yield the 180° out of phase, 2-phase clock in S
1
and S
2
. To keep D
1
=D
2
, the total delay in the S
1
path of the delay circuit
208
must equal that in the S
2
path. Thus, for the five inverter element design of
FIG. 2
, each inverter element in the S
1
path presents a delay essentially equal to (D
1
/2) whereas each element in the S
2
path has a delay of (D
1
/3). The inverter elements in each path are replicate logic inverter circuits which are designed to exhibit the particular delay shown, based upon the fixed delay D
1
=D
2
.
An important problem with the circuit design of
FIG. 2
is that in the manufactured version of the circuit, D
1
and D
2
will not precisely track each other with fabrication process, supply voltage, and temperature variations. This is in part because an inverter element in the S
1
path is designed to exhibit a different delay than one in the S
2
path, and hence these elements do not show the same change in delay as a function of process, supply, and temperature variations. As a result, D
1
may no longer be equal to D
2
when there are substantial variations in fabrication process parameters, supply voltage, and temperature. This difference can prove to be fatal to microprocessor and bus timing in high speed digital systems which require an essentially identical, very accurate and stable 2-phase clock to be available in different areas of the IC die or PWB, across a wide range of variations.


REFERENCES:
patent: 5734469 (1998-03-01), Strandjord
patent: 5867043 (1999-02-01), Kim
patent: 5945857 (1999-08-01), Havens
patent: 6292042 (2001-09-01), Kim et al.
patent: 6339354 (2002-01-01), Heightley

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