Generalized push-pull cascode logic technique

Details Generalized push-pull cascode logic technique Generalized push-pull cascode logic technique

1999-06-28

2000-11-07

Nelms, David

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

326 83, H03K 190948

Patent

active

061442283

ABSTRACT:
A method and apparatus are presented for efficient implementation of logic and arithmetic functions that generate sets of mutually exclusive output signals. Such a logic family includes a network of NMOS transistors that implements a desired logic function. Coupled to that network is a minimal number of PMOS devices for providing logic level restoration and for compensating for any voltage drops due to the NMOS transistors. With such a structure, the speed, area and power consumption characteristics of logic functions are improved.

REFERENCES:
patent: 4833347 (1989-05-01), Rabe
patent: 5023480 (1991-06-01), Gieseke et al.
patent: 5309043 (1994-05-01), Murahashi
Heller, Griffin, et al., "Cascode Voltage Switch Logic: A Differential CMOS Logic Family, "IEEE International Solid State Circuits Conference, Feb. 1984, pp. 16-17.

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