Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
1999-12-30
2003-10-14
Lee, Thomas (Department: 2185)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
C713S502000, C326S093000
Reexamination Certificate
active
06633992
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of computer systems and, more specifically, to the field of integrated circuits using pulsed clock signals.
2. Description of the Related Art
Performance goals of processors increase with every generation, and progressively more sophisticated architectures are required to implement their complex functions. Advanced architectures require long pipelines operating at very high frequencies. These higher frequencies demand increased usage of sophisticated circuit design styles like domino or dynamic circuits.
Domino circuits increase the speed performance of logic circuits by reducing the capacitance associated with the use of P-type metal oxide semiconductors (“MOS”). Domino circuits accomplish this by pre-charging a series of logic gates during a first clock phase, or pre-charge cycle, and evaluating the intended logic function during the next clock phase, or evaluation cycle.
A conventional domino or dynamic circuit typically uses one clock signal for both evaluation and pre-charge. For example, when the clock signal is high the circuit evaluates and when the clock signal is low the circuit pre-charges. Thus a circuit performs pre-charge whenever it is not evaluating.
In some implementations it may be beneficial to separate these too functions and use two separate pulsed clock signals. One pulsed clock signal controls the evaluate while the other controls the pre-charge (active low). They should not be active at the same time, or excess current will be drawn from the power supply. The pre-charge operation may be performed after each evaluation, or immediately before each evaluation. However, a problem associated with the conventional dynamic circuit is that the pre-charge operation may have to be performed hastily to prevent charge sharing failures. Reducing pre-charge time requires larger pre-charge devices, which costs circuit area, performance, and power.
Another problem associated with the conventional dynamic circuit is multiple enable signals, such as, for example, evaluate enable signal and pre-charge enable signal. A third problem associated with the conventional dynamic circuit is high soft error rate (“SER”). Soft error occurs when a pre-charged cell is inadvertently discharged due to various reasons, such as, for example, the cell is hit by cosmic rays. Soft error causes the cell to give wrong value because the cell is assumed pre-charged before the evaluation but in fact, the cell has already discharged.
SUMMARY OF THE INVENTION
A circuit has at least one input, a clock input, and an output. In one embodiment, the circuit is configured to perform a pre-charge function before an evaluate function in response to the enable input.
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Blakely , Sokoloff, Taylor & Zafman LLP
Du Thuan
Intel Corporation
Lee Thomas
LandOfFree
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