Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
2001-06-29
2004-09-28
Myers, Paul R. (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S107000, C710S058000, C710S061000
Reexamination Certificate
active
06799233
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of data communication systems, and in particular to a device and method for facilitating communications via an I
2
C bus.
2. Description of Related Art
The Inter Integrated Circuit (I
2
C) bus developed by Philips Corporation allows integrated circuits to communicate directly with each other via a simple bi-directional 2-wire (plus ground) bus. A device connects to each of the two wires on the bus, one (SDA) for the communication of data, and the other (SCL) for the control and synchronization of the communication of data between the devices. Each device is connected in parallel to each of the other devices, and each of the bus lines, SDA and SCL, function as a wired-AND of all the lines on the bus. The output of each device is configured as an open-collector/open-drain device, and one or more pull-up resistors maintain a ‘soft’ logic high value on the bus while the bus is in the quiescent state. When a device desires access to the bus, the device pulls the bus to a logic low value, via the open-collector/open-drain device that is placed in a conductive state to ground potential.
Each device that is connected to an I
2
C bus is identifiable by a unique address, and can operate as either a transmitter or a receiver, or both. Data transfers are effected using a master-slave protocol. A master is a device that initiates a data transfer and generates the clock signals to permit the transfer; any device that is addressed is considered a slave for this transfer. The data transfer can be initiated by a master to either transmit data to the slave (write), or to request data from the slave (read). A particular device can be capable of operating as either a master, a slave, or both. For example, an output device, such as a display screen, is typically not able to initiate a data transfer, and therefore would be configured to only operate as a slave device. A microprocessor, on the other hand, will typically be configured to operate as either a master or a slave, as the situation demands.
In a quiescent state, both the SDA and SCL bus lines are in the logic-high state (“high”). A master initiates a data transfer by asserting a transition to a logic-low state (“low”) on the SDA line while the SCL line is high; this is termed a START condition. Thereafter, the master toggles the SCL line to control the synchronization of the data transfer; data value changes occur on the SDA line when the SCL clock is low, and the state of the SDA line is considered valid only when the SCL clock is high. Multiple STARTs can be asserted to effect a series of data transfers within the same transfer session. Generally, each data transfer requires an acknowledgement from the addressed recipient of the data transfer. To terminate the data transfer, the host asserts a low-to-high transition on the SDA line while the SCL clock is high; this is termed a STOP condition. Thereafter, any device may assume control of the bus as a master by asserting a high-to-low transition on the SDA line, as above. Note that, for ease of reference, the term assert is used herein for effecting, or attempting to effect, the specified logic state. In the example of a transition to a logic-high state, this is typically provided by a release of the bus from a forced pull-down state by the asserting device. This assertion of a logic-high state allows the aforementioned pull-up devices on the bus to bring the bus to a logic-high state, unless another device is also forcing the pull-down state.
The general format of an I
2
C data transfer is illustrated in
FIG. 1
, which illustrates the signals on an SDA line and an SCL line forming the I
2
C bus. A START condition (S) is illustrated at
110
, corresponding to high-to-low transition of the signal on the SDA line while the SCL line is high. After the START, the host transmits an address
120
, nominally seven bits, followed by a read/write-not indicator
130
. After transmitting the address
120
and the direction of data transfer (R/W-)
130
, the host releases the SDA line, allowing it to rise to a logic-high level. If a slave device recognizes its address, the slave device transmits an acknowledge signal (ACK)
140
by pulling the bus low. The absence of a low signal when the host releases the SDA line, therefore, indicates a non-acknowledgement (NAK). If the address
120
is acknowledged, via a low at
140
, the transmitting device transmits the data
150
. If the direction of data transfer is a “read” relative to the host, then the slave device is the transmitting device; if the direction is a “write” relative to the host, then the master device is the transmitting device. The transmitting device releases control of the SDA line, and the receiving device acknowledges the receipt of the data
150
by asserting a logic-low value on the SDA line, at
160
. If the data is acknowledged, the transmitter sends additional data
170
. This process continues until the entirety of the data is communicated, or until a transmitted data item is not-acknowledged, as indicated at
180
. The master can subsequently reassert a START signal (not illustrated), and repeat the process above, or, can assert a STOP signal (P)
190
to terminate this data-transfer session.
The above interface protocol can be implemented in a variety of ways. To minimize the development time for programming or designing an I
2
C interface, a variety of general-purpose interface schemes have been published. “DESIGN OF A BEHAVIORAL (REGISTER TRANSFER LEVEL, RTL) MODEL OF THE INTER-INTEGRATED CIRCUIT OR I
2
C-BUS MASTER-SLAVE INTERFACE”, Master's Thesis of Amrita Deshpande, University of New Mexico, 1999, discloses an I
2
C master interface and slave interface that is intended to be embodied in an I
2
C device, and is incorporated by reference herein. By providing a verified I
2
C interface, system designers need not address the details of the I
2
C specification and protocol. Both the master and the slave interfaces of this thesis are state-machine based.
A state-diagram
200
corresponding to the I
2
C slave protocol of the referenced thesis is illustrated in FIG.
2
. The state diagram
200
comprises six states, A-F, and state transitions are effected on the active edge (0-to-1 transition) of the SCL clock signal from the master. That is, in accordance with the I
2
C specification, the master controls the sequence and synchronization of operations on the bus by controlling the SCL clock line. A slave device must operate in synchronization with the master device, such that transitions on the SDA line only occur while the SCL line is low, and such that valid data is present on the SDA line for the duration of the high state on the SCL line.
A reset signal, typically a power-on reset, brings the interface to state A, the idle state. When a START condition is detected, the interface enters state B, where it receives the aforementioned (
FIG. 1
) address
120
and data-direction
130
information from the host. If the received slave address does not match the address associated with the particular interface
200
, the interface returns to the idle state A. If the data-direction
130
is read, the interface enters state C; otherwise, if the data-direction
130
is write, the interface enters state E. When the interface enters state C or state E, it acknowledges the receipt of its address and the data-direction, and prepares the interface for the required read or write operation. As noted above, the read and write directions are relative to the master device. Therefore, at the slave device, a read corresponds to a request for the slave to transmit data to the master for reading, and a write corresponds to a request for the slave to receive data written from the master.
In state C, the data that is to be transmitted to the master is loaded, and the interface transitions to state D, wherein it transmits the loaded data to the master. If the master acknowledges the receipt of the data, the interface re-enters state C; otherwise, it re-enters
Andrews Paul
Deshpande Amrita
Koninklijke Philips Electronics , N.V.
Myers Paul R.
Phan Raymond N
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