General purpose delay logic

Details General purpose delay logic General purpose delay logic

2008-04-29

2008-04-29

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S099000, C326S113000

Reexamination Certificate

active

11207635

ABSTRACT:
A logic circuit for delaying a signal input thereto by a number of clock cycles X is described. In one embodiment, the logic circuit comprises a demultiplexer (“DEMUX”) which includes an input for receiving the signal and N outputs; a register array comprising at least X registers, wherein each of the N outputs of the DEMUX is connected to a corresponding one of the X registers; and a multiplexer (“MUX”) comprising M inputs, wherein each of the M inputs is connected to one of the registers.

REFERENCES:
patent: 6539034 (2003-03-01), Shimosaka

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