General purpose bus with programmable timing

Details General purpose bus with programmable timing General purpose bus with programmable timing

1999-08-23

2002-12-03

Gaffin, Jeffrey A. (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Peripheral monitoring

C710S016000, C710S058000, C710S060000, C710S305000, C710S307000, C710S313000, C710S315000, C713S501000

Reexamination Certificate

active

06490638

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to bus architectures within systems, and more particularly to a general purpose bus with programmable timing capability.
2. Description of the Related Art
A bus provides a mechanism for communication between components of a system or microcontroller. A bus is essentially a collection of wires through which data may be transmitted from one part of a system to another part of the system. In a computer system, for example, a bus connects all the internal components of the computer to the central processing unit, or CPU, and to main memory.
Buses are generally thought to be made up of three elements: an address portion, or address bus, a data portion, or data bus, and a control portion, or control bus. The address bus specifies the location from where the data is either retrieved or submitted. The data bus transfers the actual data. The control bus contains control signals which coordinate activities between the sender, the receiver, and between the address and data buses as well. For example, one signal of the control bus may indicate whether the processor is currently reading from or writing to main memory. Another signal of the control bus may indicate whether an I/O port or main memory is being accessed.
A bus cycle can be viewed as a complete set of operations necessary between the address, data and control buses in order for a command to be processed in a system. Because a system may include a variety of components with different requirements, these components may run at different speeds. Buses are typically designed to run with fixed timing and a fixed protocol. Peripheral components with timing and protocols different from the bus may therefore not be connected to the bus. Accordingly, to support a particular peripheral component, a bus design typically may not support other peripheral components whose timing and protocol requirements differ.
One of the better known buses for personal computers is known as the industry standard architecture, or ISA, bus. The first ISA bus was 8 bits wide and ran at 4.77 MHz. Then, it was changed to a 16-bit data width and its clock speed was increased to 8 MHz. The desire to support devices which depend on these criteria has kept the ISA standard from improving since 1984.
SUMMARY OF THE INVENTION
Briefly, the illustrative system provides a general purpose bus with programmable timing capability. This general purpose bus provides a mechanism for communication between external components connected to the bus and other parts of the system or microcontroller. Because the general purpose bus is programmable, peripheral components with different timing and protocol requirements may simultaneously occupy the bus. Thus, for example, both ISA bus peripherals which run at 4.77 MHz and those which run at 8 MHz can be connected to the general purpose bus. Further, for embedded system designs which so desire, the general purpose bus may be programmed to emulate an ISA bus.
In one embodiment, a microcontroller includes peripheral components, such as UARTs, a watchdog timer, a real-time clock, and a programmable interrupt controller, all of which are internal to the microcontroller. These internal peripheral components are connected to the general purpose bus. Additionally, the microcontroller supports the connection of external peripheral components, also using the general purpose bus. Accordingly, the general purpose bus of the illustrative system includes an internal and an external portion.
The general purpose bus is coupled to a general purpose bus controller which includes registers for programmable timing of the bus. These registers provide the capability to program the bus cycle length for several signals which are used to communicate with external devices connected to the general purpose bus. In one embodiment, these programmable signals include eight chip selects, to support up to eight external peripheral devices. Additionally, read strobes for both memory and I/O read commands, write strobes for both memory and I/O writes, and address latch enable signals are programmable for each external peripheral component connected to the bus.
By programming the registers of the general purpose bus controller, a customized bus cycle for external peripheral components is provided. The registers enable programming of the offset, the pulse width, and the recovery time, resulting in a preferred bus cycle length for each external device. In the disclosed embodiment, the bus cycle may be as short as 90 nanoseconds or as long as 23 microseconds.
Additionally, the general purpose bus provides an echo mode which is useful for debugging. In the disclosed embodiment, the general purpose bus controller provides one programmable timing set for the external peripheral devices and one fixed timing set for the internal peripheral devices. However, when the echo mode is enabled, the internal general purpose bus cycle is echoed out on the external pins of the microcontroller, making the signal available to logic analyzer or other debugging equipment. During echo mode, accesses to internal peripheral devices utilize the programmed timing set. This ensures that no timing conflict with other external peripheral devices occurs.
By including this flexible bus in a microcontroller, external peripheral devices may be coupled to the microcontroller architecture with relative ease. In particular, embedded system designers may connect peripheral devices using no additional real estate, such as programmable array or other glue logic. Such peripheral components may include single-function chips, such as a programmable interrupt controller, or a programmable interval timer. Additionally, this flexible bus may support multi-function chips, such as a super I/O controller or a serial communications controller. For each of these peripheral components, the bus cycle may be programmed to suit the timing requirements of the external device, thus optimizing the throughput of the system.


REFERENCES:
patent: 4523274 (1985-06-01), Fukunaga et al.
patent: 5175820 (1992-12-01), Gephardt
patent: 5428746 (1995-06-01), Dalrymple
patent: 5548766 (1996-08-01), Kaneko et al.
patent: 5630108 (1997-05-01), Wichman et al.
patent: 6070205 (2000-05-01), Kato et al.
patent: 6134638 (2000-10-01), Olarig et al.
patent: 6260098 (2001-07-01), Ku
ISA System Architecture, Tom Shanley & Don Anderson, 1995, pp. 21 through 26, 139 through 151, and 335 through 362.
Élan ™ SC400 and Élan ™ SC410 Single-Chip, Low-Power, PC/AT-Compatible Microcontrollers, Data Sheet, Advanced Micro Devices, Inc., Dec. 1998, pp. 1 through 132.

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