Electric lamp and discharge devices – Discharge devices having a multipointed or serrated edge...
Reexamination Certificate
2000-10-06
2003-12-16
Kim, Robert H. (Department: 2882)
Electric lamp and discharge devices
Discharge devices having a multipointed or serrated edge...
C313S326000, C313S351000
Reexamination Certificate
active
06664721
ABSTRACT:
TECHNICAL FIELD OF THE DISCLOSURE
The present disclosure relates in general to electron field emitters and, more particularly, to a method and system for improved electron field emission with an interlayer between the emitting material and a dielectric layer.
BACKGROUND
Gated field emitter arrays show promise for use in many electronic products including electron guns for cathode ray tubes used in computer monitors and other display devices. One method of manufacturing gated field emitter arrays uses a process that includes deposition of dielectrics and metals on the emitter material then etching back portions of the deposited materials around the protrusions or tips where electron emission occurs. For example, a wafer of an emitter material such as sp
2
and sp
3
bonded carbon can be formed with microtips on the wafer surface. Such emitters are described in co-pending and commonly assigned patent applications Ser. No. 09/169,908 and Ser. No. 09/169,909, which are hereby incorporated by reference herein. A conventional deposition tool such as a sputter deposition system or a plasma enhanced chemical vapor deposition (PECVD) can then deposit a conformal dielectric film on the wafer. One such dielectric is silicon dioxide (SiO
2
). A thin conductive gate layer is then deposited on top of the dielectric film. To form the gate holes with this process an aluminum hard mask is sputter deposited on the gate layer. Next, a layer of photoresist is deposited on the emitter/dielectric/gate layer/hard mask stack using a spinner so that the resist is thinner above the microtips than elsewhere across the wafer.
After depositing the layers, selective ion etching can be used to thin the photoresist such that the thin photoresist, in the area above the microtips, is completely removed. The thicker photoresist on the wafer between the microtips is thinned, but not removed. The surface is then exposed to a chemical etchant that removes the hard mask and conductive gate layer in the areas where the photoresist has been removed, i.e., over the microtips. A combination of conventional wet chemical etch and dry etch techniques can then be used to remove the exposed dielectric from the tips and then the remaining photoresist and hard mask to form the gated structure.
Using the gate-forming scheme described above, conventional dielectrics like silicon nitride and silicon dioxide can intermix with the emitter material during dielectric deposition. For example, during sputtering of the dielectric layer, silicon dioxide can intermix with the carbon atoms that form the emitter material. This intermixed layer may remain during the etch step that forms the gate, thereby changing the emission properties of the emitter material. If the intermixed layer is too thick it may significantly increase the electric field necessary for electron emission, detrimentally affecting the performance of the device. An example of the result of intermixing is shown in FIG.
1
.
FIG. 1
illustrates the performance difference between emitter tips before dielectric deposition and after dielectric deposition and sebsequent dielectric removal with buffered hydroflouric acid (BHF). Clean carbon tips, formed by process described and claimed in co-pending and commonly assigned patent application Ser. No. 09/169,909, filed Oct. 12, 1998, which is hereby incorporated by reference herein, were used to obtain the data in curve
6
of FIG.
1
. Using well known techniques, an electrically conducting ball having a large radius compared to the tips array size was lowered over the surface of the tips and voltage applied to obtain emission current at different values of applied voltage. Curve
6
of
FIG. 1
illustrates diode emission current that results from a range of electric fields across an ungated microtip array of carbon tips. Curve
8
illustrates the experimental relationship between electric field and emission current for carbon tips after silicon dioxide had been sputter deposited at 400 watts of RF power and then etched away with buffered hydrofluoric acid. The electric field required to obtain high levels of emission current is more than doubled for the carbon emitter after formation and removal of the silicon dioxide layer.
When intermixing occurs between the emitter material and the dielectric layer, there is need for a structure and method of manufacturing that will decrease or eliminate the negative effects of an intermixed layer.
SUMMARY OF THE INVENTION
A system and method for separating a dielectric layer and a field emitter with an interlayer. None of the advantages disclosed, by itself, is critical or necessary to the disclosure.
A disclosed system includes a field emitter layer having a plurality of microtips. Attached to the field emitter layer is an interlayer. The interlayer contains openings above at least a majority of the microtips. The interlayer material adheres well to the emitting material without significant intermixing. A dielectric layer is deposited on the interlayer on the opposite side from the field emitter layer and contains openings above at least a majority of the microtips. A conductive gate layer is deposited on the dielectric layer on the other side from the interlayer. The conductive gate layer has openings above at least a majority of the microtips.
A more specific system is also provided in which the field emitter layer is formed of a carbon-based material, the dielectric is formed of silicon dioxide, and the interlayer is formed of aluminum. As an alternative the interlayer could be formed of another metal, including but not limited to gold or platinum.
A more specific system is also provided in which the interlayer can be selectively etched without etching the dielectric layer, the field emitter layer, or the conductive gate layer.
A method is provided for forming an improved electron emitter by separating a dielectric and a field emitter with an interlayer. A wafer of a field emitter material, having a plurality of protrusions extending from a planar surface, is provided. An interlayer material is deposited on the wafer. A dielectric material is then deposited on the interlayer material. A conductive gate layer is then deposited on the dielectric layer. A hard mask is then deposited on the conductive gate layer. A photoresist layer is spun on the hard mask layer such that the photoresist layer is thinner above the wafer protrusions than elsewhere. The photoresist layer is etched through its thinner, but not thicker, areas. The exposed layers above the protrusions are etched in sequence to expose at least the tops of the protrusions on the surface of the wafer.
A more specific method is also provided in which the step of depositing the interlayer comprises sputter depositing aluminum at a deposition power of between 790 and 810 watts for between 20 and 30 seconds in 2-5 millitorr of argon.
It is a technical advantage of the disclosed systems and methods that electrons can be emitted from the ends of the microtips or protrusions of the field emitter layer at lower values of electric field.
It is also a technical advantage of the disclosed systems and methods that the microtips or protrusions maintain their initial emission characteristics after deposition and etching of other layers.
Another technical advantage of the systems and methods disclosed is that any stresses (thermal, mechanical etc.) between the emitter material and the dielectric layer are more effectively managed by the stress relaxation properties of the interlayer.
REFERENCES:
patent: 4964946 (1990-10-01), Gray et al.
patent: 5401676 (1995-03-01), Lee
patent: 6031250 (2000-02-01), Brandes et al.
patent: 6297587 (2001-10-01), Kikuchi et al.
patent: 6417606 (2002-07-01), Nakamoto et al.
Kim, et al., “Fabrication of silicon field emitters by forming porous silicon,” Journal of Vacuum Science and Technology: Part B, vol. 14, No. 3: pp. 1906-1909, 1996.
Hebert David F.
Hong Charlie
Jamison Keith D.
Patterson Donald E.
Schueller Randolph D.
Baker & Botts L.L.P.
Extreme Devices Incorporated
Kim Robert H.
Yun Jurie
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