Gate voltage testkey for isolation transistor

Details Gate voltage testkey for isolation transistor Gate voltage testkey for isolation transistor

2001-02-27

2001-10-09

Fears, Terrell W. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Testing

C365S208000

Reexamination Certificate

active

06301172

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates in general to a semiconductor device and in particular to a semiconductor device incorporating a gate voltage testkey for selectively programming isolation transistor gate voltage.
DRAM memory has enjoyed popular success over other types of memory technology because of its low cost and simple memory cell layout which promotes scalability. A DRAM memory cell is capable of storing one bit of information, and is constructed using only one memory cell transistor and one memory cell capacitor. As such, this memory cell is often referred to as a one-transistor one-capacitor (1T1C) cell. A collection of memory cells are grouped together in bitlines and wordlines, forming a memory array.
While device density in DRAM memory is limited by the resolution capability of available photolithographic equipment, it is also limited by the area consumed by each of the memory cells. Referring to
FIG. 1
, a memory structure
10
is comprised of a plurality of memory cells
12
. As identified herein, the minimum area of a memory cell
12
is defined with reference to a feature dimension (F) which refers to the dimension that is half the wordline WL pitch (width plus space) or half the digitline DL pitch (width plus space). To illustrate the determination of cell area, a box is drawn around the memory cell
12
. Along the horizontal axis H of the memory cell
12
, the box includes one-half digitline contact feature
14
, one wordline feature
16
, one capacitor feature
18
and one-half field oxide feature
20
, totaling three features. Along the vertical axis V of the memory cell
12
, the box contains one half field oxide feature
22
, one active area feature
24
, and a second half oxide feature
26
totaling two features. The structure of the memory cell
12
results in its area being 3F.multidot.2F or 6FSupp2. To conserve space on a die, memory cell pairs
28
are defined by adjacent memory cells
12
that share a single bitline contact
30
.
While the 6Fsupp2 array may be implemented as an open bitline as well as a folded bitline, early memory devices incorporated the open bitline configuration. In the open bitline architecture, each wordline connects to memory cell transistors on every bitline. This is sometimes referred to as a crosspoint style array. Referring to
FIG. 2
, a memory structure
100
is illustrated for an open digitline architecture. The memory structure
100
includes a plurality of memory cells
102
. Each memory cell
102
is comprised of a capacitor
104
, having a common node
106
biased at a voltage of Vcc/2 volts. The capacitor
104
typically represents a binary logic level one by a charge of +Vcc/2 volts, and a binary logic level zero by a charge of −Vcc/2 volts. Each memory cell
102
is further comprised of a transistor
108
having a first source/drain region
110
, a second source/drain region
112
, and a gate
114
. The gate
114
of each transistor
108
connects to a wordline (WL)
1
16
,
118
,
120
,
122
,
124
and
126
. Further, the first source/drain region
110
of each transistor
108
connects to a bitline (BL)
128
.
As demands for higher capacity memory devices continue to increase, memory cells are placed closer together. However, where memory cells of a conventional 6 Fsupp2 array are packed too closely, adjacent memory cells may be affected by subthreshold leakage. Excessive subthreshold leakage may affect data integrity. In an attempt to resolve the problems that are attributable to the conventional 6 Fsupp2 array, the industry adopted an 8 Fsupp2 array where improved noise performance is realized by providing a twisted configuration. The 8 Fsupp2 memory array is created by tiling a selected quantity of memory cells together such that memory cells along a given bitline do not share a common wordline and such that memory cells along a common wordline do not share a common bitline. Any given wordline forms a memory cell transistor on alternating bitlines. This structure allows the formation of bitline pairs and ensures that wordline activation enables transistors only on alternate bitlines. Further, the 8 Fsupp2 provides improved noise performance, which is derived from the adjacency of true and complement bitlines and the capability to twist these bitline pairs. However, since the wordlines have to pass alternate memory cells as field poly, the size is increased by approximately 25%, or by 2 features. As such, the 8 Fsupp2 array does not provide the same degree of packing density seen in the 6 Fsupp2 array described above. As the demand for memory devices with larger capacity continues to increase, the larger array size provided by the 8 Fsupp2 array become a limiting factor.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a 6 Fsupp2 area array with improved subthreshold leakage characteristics, which allows for a higher packing density thus more densely populated memories.
SUMMARY OF THE INVENTION
The present invention overcomes the disadvantages of previously known 6 Fsupp2 array architectures by providing a programmable gate voltage to minimize subthreshold leakage of an isolation transistor positioned between adjacent memory cells.
The memory cell is thoroughly tested using a testkey device, which is capable of testing different isolation gate voltages on the fly, without the need to create a reticle to change the gate voltage. The testkey is such that a fair comparison of data collected from the same array space can be realized. Further, upon determining that the measured subthreshold leakage for a particular bit is excessive, the isolation transistor gate can be permanently changed from ground, or zero volts to the back bias voltage (Vbb), or some other voltage more negative than ground to effectively shut the transistor off harder. The testkey may selectively test alternative negative potentials, until the subthreshold leakage is brought within satisfactory parameters. Once the required isolation gate potential has been determined, it may optionally be permanently programmed to that potential, using an antifuse device.
In a first embodiment of the present invention, a memory device has an array of storage cells having a plurality of selectively addressable memory cells coupled to a bitline, and isolation devices positioned to prevent leakage between the plurality of selectively addressable memory cells, each of the isolation devices having an isolation control. A test circuit is coupled to the array of storage cells, and is capable of determining characteristics of the isolation devices. A translator is coupled to the test circuit, and has a bias control coupled to each of the isolation controls. The translator is programmable to provide one of at least two bias signals to the isolation controls.
Preferably, the isolation device comprises an isolation transistor, and the isolation control comprises a gate of the isolation transistor. Under this arrangement, the translator bias control is coupled to the gate of the isolation transistor, and the translator is programmable to provide one of at least two voltages to the gate of the isolation transistors, each of the at least two voltages are biased to turn off the isolation transistors. The present embodiment can be realized in a 6 Fsupp2 array, in an open or closed bitline architecture where the array of storage cells further comprises a plurality of bitlines, and the plurality of selectively addressable memory cells further comprises a plurality of adjacent storage cell pairs connected to each of the plurality of bitlines, and the isolation transistors are positioned to provide isolation between each of the plurality of adjacent storage cell pairs.
While the chip is in the test mode, the testkey is capable of determining the isolation gate voltage needed for the isolation transistors to remain off. When the chip is not being tested, a device such as an antifuse

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