Gate-to-drain overlapped MOS transistor fabrication process

Details Gate-to-drain overlapped MOS transistor fabrication process Gate-to-drain overlapped MOS transistor fabrication process

1991-07-05

1993-10-26

Wilczewski, Mary

Fishing, trapping, and vermin destroying

437 41, 437233, 257336, H01L 21336

Patent

active

052565866

ABSTRACT:
A method for fabricating a gate-to-drain overlapped MOS transistor in which gate-to-drain capacitance is lower and a structure thereby. A pad oxide layer is formed over a substrate having a first conductive layer with a first pattern formed on a first gate oxide layer, and etchback process is performed until surface part and a predetermined upper parts of the both side walls of the first conductive layer is exposed. As a result, a second conductive layers with a second pattern is formed and a second gate oxide layer thicker than the first gate oxide layer is formed.

REFERENCES:
patent: 5013675 (1991-05-01), Shen et al.
patent: 5024959 (1991-06-01), Pfiester
patent: 5120673 (1992-06-01), Itoh

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