Gate structure of semiconductor memory device

Details Gate structure of semiconductor memory device Gate structure of semiconductor memory device

2006-12-05

2006-12-05

Lee, Hsien-Ming (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S412000, C257S413000, C257SE21623, C438S652000

Reexamination Certificate

active

07145207

ABSTRACT:
A gate structure of a semiconductor memory device capable of preventing a poly void generation by forming a hard mask and maintaining a hysteresis area within a certain value. The gate structure of the semiconductor memory device includes: a gate insulation layer formed on a semiconductor substrate; a gate electrode formed on the gate insulation layer, wherein the gate electrode is formed by stacking a polysilicon layer and a metal layer; and a hard mask formed on the gate electrode, wherein a hysteresis area between the hard mask and the gate electrode materials is a equal to or less than approximately 2×1012° C.-dyne/cm2.

REFERENCES:
patent: 2002/0086507 (2002-07-01), Park et al.

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