Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-05-12
2001-09-18
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S410000
Reexamination Certificate
active
06291864
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to high density semiconductor devices, and in particular, to a method for forming a gate structure having a polysilicon layer with recessed side portions for reducing parasitic capacitance of the gate.
BACKGROUND OF THE INVENTION
There is a constant push in the semiconductor industry towards reducing the size of semiconductor integrated circuits (ICs), which requires the reduction in semiconductor device geometry and interconnect lines connecting the semiconductor devices. Furthermore, the spacing between interconnect lines and adjacent semiconductor devices must also be reduced to fully achieve smaller ICs. However, as the spacing between interconnect lines and semiconductor devices is reduced to the micron and submicron range, a parasitic intra-level capacitance between the interconnect lines and adjacent devices increases. Consequently, in order to reduce cross-talk between interconnect lines and semiconductor devices and to maximize semiconductor device speed it becomes increasingly important to reduce the parasitic capacitance between interconnect lines and semiconductor devices. In fact, in many cases, the intra-level capacitance of metal interconnect lines has become the limiting factor in determining the speed of many silicon ICs.
One approach to reduce the intra-level capacitance involves increasing the spacing between the interconnect lines and adjacent semiconductor devices. However, this proposed solution is not compatible with the original goal of shrinking the size of semiconductor ICs.
A second approach to reduce the intra-level capacitance involves using a low dielectric constant material between the interconnect lines and adjacent semiconductor devices. A third approach involves depositing a first dielectric layer, etching away the initial dielectric material deposited between the interconnect lines and the semiconductor devices, and refilling the etched away portion with a different low dielectric constant polymer. The second and third proposed solutions produce detrimental side effects and may not sufficiently reduce the intra-level capacitance of the IC. With the use of increasingly small spacing between the interconnect lines and semiconductor devices, the low dielectric constants of many dielectric materials are often not low enough to significantly reduce the parasitic inter-level capacitance. Moreover, the process steps associated with incorporating these dielectrics into a conventional process flow are time consuming, complicated, and expensive. The resulting structure also may reduce the efficiency of heat dissipation since materials having lower dielectric constants generally have lower thermal conductivity. Furthermore, the resulting structure creates other reliability problems that include, but are not limited to, moisture absorption, adhesion failures, and mechanical stress failures.
Thus, there is a need for improved structures that reduce the parasitic capacitance between interconnect lines and adjacent semiconductor devices without the drawbacks described above. Accordingly, a need exists for a device that is structurally sound, is not expensive to manufacture and does not cause a significant increase in the cycle time of the manufacturing process flow. The method should also not impede thermal dissipation and should be compatible with shrinking the size of semiconductor ICs.
SUMMARY OF THE INVENTION
The present invention provides a device and method for reducing parasitic capacitance between the gate and an adjacent conductive layer. The present invention achieves a reduction in intra-level parasitic capacitance by providing a gate structure having a polysilicon layer with recessed side portions.
The present invention advantageously provides an embodiment that includes sidewalls or spacers to partially cover the sides of the polysilicon layer, while the exposed side portions of the polysilicon layer are etched to form the recessed side portions. The area that is etched away to form the recessed side portions accounts for the reduction in intra-level parasitic capacitance between the gate and the adjacent conductive layer. By removing the area etched away to form the recessed side portions, the present invention increases the separation between the gate and any nearby conductive layers, such as local interconnect layers, interconnect layers, and contact layers, thereby inhibiting parasitic capacitance which, among other factors, is a function of the distance between two electrical components. Consequently, the present invention provides a simple device and method of reducing the parasitic capacitance of the semiconductor device without sacrificing valuable semiconductor space.
Additional advantages and other features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention. The advantages of the invention may be realized and obtained as particularly pointed out in the appended claims.
REFERENCES:
patent: 5053849 (1991-10-01), Izawa et al.
patent: 5641712 (1997-06-01), Grivna et al.
Huang et al, “A new LDO . . . Inverse T-Gate Structure,” IEEE Electron Dev Letters, vol EDL 8, #4, 4/1987, pp. 151-153
Advanced Micro Devices , Inc.
Meier Stephen D.
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