Gate structure for integrated circuit fabrication

Details Gate structure for integrated circuit fabrication Gate structure for integrated circuit fabrication

1999-06-25

2001-11-20

Crane, Sara (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S295000, C257S310000, C257S411000

Reexamination Certificate

active

06320238

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a gate stack structure for integrated circuits and its method of manufacture.
BACKGROUND OF THE INVENTION
Giga-scale electronic device integration and miniaturization has resulted in 0.25 micron (and smaller) minimum device feature size. In many memory circuits, the metal oxide semiconductor (MOS) transistor is employed along with capacitors. As device miniaturization continues, the gate length and the capacitor plate area are reduced. In the transistor, this reduced feature size can reduce the device transconductance, while in a capacitor, the capacitance can be reduced to an unacceptable level. To this end, the capacitance of storage capacitors in dynamic memories, for example, is reduced with the reduced feature sizes, and the memory cells may become error prone.
As can be readily appreciated by one of ordinary skill in the art, the gate structure of a MOS transistor approximates a parallel plate capacitor, with the gate and semiconductor substrate forming the electrodes thereof. It is desired to compensate for the reduced capacitance that results from the reduced feature sizes in order to maintain (if not increase) the transconductance and to maintain (if not reduce) the threshold voltage of the MOS field effect transistor.
In order to maintain or increase the capacitance (of the MOS transistor or the storage capacitor with reduced plate area), it is necessary either to decrease the spacing between the electrodes of the capacitor or to use a material having a higher dielectric constant. Unfortunately, conventional dielectrics such as ultra-thin (less than 3.5 nm) silicon dioxide layers have hindered the effort to reduce the spacing between the electrodes. For example, as the tunneling limit of 2.5 nm for silicon dioxide is approached, tunneling currents exceed acceptable values. By using materials having a higher dielectric constant than silicon dioxide, the desired capacitance may be achieved, while the problems of leakage currents and processing difficulties associated with dimensionally thin dielectrics may be diminished.
One example of the use of high dielectric constant stacked gate dielectric structures is disclosed in the above-captioned parent application to L. C. Kizilyalli et al. One embodiment disclosed in the application to Kizilyalli, et al. has a layer of silicon dioxide grown and densified on an oxidizable substrate; a layer of high dielectric constant (high-k) material; and a deposited layer of silicon dioxide disposed on the high dielectric constant material. The deposited oxide layer is used, among other reasons, as a “buffer” layer between the high-k material and the polysilicon gate electrode disposed on the deposited silicon dioxide layer. For example when the high-k layer is tantalum pentoxide, the deposited SiO
2
layer buffers the high-k layer from the polysilicon gate, preventing reduction of the tantalum pentoxide by the polysilicon layer. This prevents consequential elemental tantalum in the high-k layer, and undesired shorting in the high-k layer. Transistors using the stacked gate dielectric material of the parent application have characteristics of a low concentration of interface trap sites, an improved tunneling voltage, negligible fixed charge (Q
f
), improved interface carrier mobility, and a low effective dielectric thickness compared to other conventional structures.
While the dielectric stack for use as the gate structure in a MOSFET or as a storage capacitor in an integrated circuit of the parent application has facilitated miniaturization by compensating for reduced feature size, there is a need to even further reduce feature size. As discussed above, there is a need to reduce the dielectric thickness to facilitate device scaling and integration, in general. While the reduction in dielectric thickness of conventional materials, such as silicon dioxide, will increase the capacitance, there is a lower limit on silicon dioxide thickness were deleterious electrical effects are encountered. Accordingly, it is desired to have dielectric material(s) which result in the same capacitance as a particular thickness of silicon dioxide, but which can be processed with less complications and which do not suffer from the electrical shortcomings of ultra-thin layers of silicon dioxide. Further, what is needed is a dielectric structure, and its method of fabrication which enables a further reduction in feature size and thus an increase in integration/miniaturization, while avoiding the problems of ultra-thin layers of silicon dioxide used in conventional structures.
SUMMARY OF THE INVENTION
The present invention relates to a gate stack structure and its method of manufacture having a dielectric material layer disposed over a substrate with a gate electrode disposed over the dielectric material layer. In an exemplary embodiment, the dielectric material layer has an equivalent electrical thickness of 2.2 nm or less and includes at least one layer other than silicon dioxide. The structure is fabricated by disposing a grown oxide layer on a substrate, disposing at least one layer of high-k dielectric thereover, and disposing a conductive layer directly on the high-k layer.


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“Stacked High-&egr; Gate Dielectric For Gigascale Integration Of Metal-Oxide-Semiconductor Technologies”, P.K. Roy et al.,Applied Physics Letter, vol. 72, No. 22, Jun. 1, 1998, pp. 2835-2837.
“MOS Transistors With Stacked SiO2-Ta2O5-SiO2 Gate Dielectrics For Giga-scale Integration Of CMOS Technologies”, I.C. Kizilyalli et al.,IEEE Electron Device Letters, vol. 19, No. 11, Nov. 1998, pp. 423-425.
“Characterization Of Stacked Gate Oxides By Electron Holography,” W. D. Rau et al., Applied Physics Letters 68 (24), Jun. 10, 1996.

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