Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-09-27
2004-08-31
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S411000, C257S616000
Reexamination Certificate
active
06784507
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to electronic semiconductor devices, and, more particularly, to integrated circuit dielectric structures and fabrication methods.
The trend in semiconductor integrated circuits to higher device densities by down-scaling structure sizes and operating voltages has led to silicon field effect (MOS) transistor gate dielectrics, typically made of silicon dioxide, to approach thicknesses on the order of 1-2 nm to maintain the capacitive coupling of the gate to the channel. However, such thin oxides present leakage current problems due to carrier tunneling through the oxide. Consequently, alternative gate dielectrics with greater dielectric constants to permit greater physical thicknesses have been proposed. Indeed, Ta
2
O
5
, (Ba,Sr)TiO
3
, and other high dielectric constant materials have been suggested, but such materials have poor interface stability with silicon.
Wilk and Wallace, Electrical Properties of Hafnium Silicate Gate Dielectrics Deposited Directly on Silicon, 74 Appl. Phys. Lett. 2854 (1999), disclose measurements on capacitors with a hafnium silicate dielectric formed by sputtering deposition (at a pressure of 5×10
−6
mTorr and substrate temperature of 500 C) of a 5 nm thick Hf
6
Si
29
O
65
(Hf
0.37
Si
1.78
O
4
) layer directly onto silicon together with a gold top electrode on the silicate dielectric. Such capacitors showed low leakage current, thermal stability, an effective dielectric constant of about 11, and a breakdown field of 10 MV/cm.
Another approach to enhanced performance for silicon integrated circuits uses Si
x
Ge
1−x
layers on silicon substrates to achieve higher hole mobilities for PMOS plus provide heterojunction bipolar transistors (HBTs). Sharma et al, Properties of Gate Quality Silicon Dioxide Films Deposited on Si—Ge Using Remote Plasma-Enhanced Chemical Vapor Deposition, 17 JVST B 460 (2000) describe measurements on capacitors with silicon dioxide dielectric on Si
x
Ge
1−x
layers of thickness 20-40 nm and with x in the range of 0.85-0.9. Similarly, Ngai et al, Electrical Properties of ZrO
2
Gate Dielectric on SiGe, 76 Appl.Phy.Lett. 502 (2000) reveals measurements of capacitors with 3-8 nm thick ZrO
2
dielectric on 40 nm thick layers of Si
0.85
Ge
0.15
on silicon.
However, such dielectrics have problems with interfacial layers formed at the dielectric-SiGe interface.
Alternative SiGe approaches deposit a thin buffer Si layer on the SiGe in order to form SiO
2
gate dielectric, but such approaches fail to achieve the full advantage of the increased mobility of SiGe.
SUMMARY OF THE INVENTION
The present invention provides integrated circuit fabrication with metal silicate or silicate-germanate dielectrics for SiGe and Si surfaces without buffer layers.
This has advantages including improved performance CMOS integrated circuits with simple processing.
REFERENCES:
patent: 6437392 (2002-08-01), Schneemeyer et al.
patent: 6544875 (2003-04-01), Wilk
Gnade Bruce E.
Wallace Robert M.
Brady W. James
Hoel Carlton H.
Prenty Mark V.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
LandOfFree
Gate structure and method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Gate structure and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Gate structure and method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3297021