Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-03-03
2001-08-28
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S412000, C257S616000
Reexamination Certificate
active
06281559
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to an integrated circuit (IC) and the fabrication of an integrated circuit. More particularly, the present invention relates to the formation of a gate stack having a compound semiconductor gate layer.
BACKGROUND OF THE INVENTION
Ultra-large-scale integrated (ULSI) circuits generally include a multitude of transistors, such as, more than one million transistors and even several million or more transistors, that cooperate to perform various functions for an electronic component. Some transistors on the integrated circuit (IC) or chip are part of circuits which perform different operations within other circuits.
Some transistors perform functions for circuits in the critical signal path of the IC, where speed is crucial to the proper operation of the IC. In contrast, other transistors perform functions for circuits in the non-critical signal path of the IC, where speed is not as important. Transistors in the non-critical signal path are preferably designed to consume less power than transistors in the critical signal path. Still other transistors may perform functions for a signal path having a criticality somewhere between the critical signal path and the non-critical signal path and, accordingly, have different speed and power consumption requirements.
Due to smaller off-state current leakage, transistors which have higher threshold voltages (Vth) generally consume less power than transistors which have lower threshold voltages. Threshold voltage refers to the minimum gate voltage necessary for the onset of current flow between the source and the drain of a transistor. Transistors which have lower threshold voltages are faster (e.g., have quicker switching speeds) than transistors which have higher threshold voltages.
In ULSI circuits, transistors, such as, metal oxide semiconductor field effect transistors (MOSFETs) with low threshold voltages, can be used in logic paths which have high speed requirements. In contrast, transistors, such as, MOSFETs with higher threshold voltages, can be used in the non-critical signal path (e.g., storage devices), thereby reducing the off-state leakage current and, hence, reducing the standby power consumption of the entire IC.
ULSI circuits are generally manufactured in accordance with complementary metal oxide semiconductor (CMOS) technology and design criteria which utilize N-channel MOSFETs and P-channel MOSFETs. The N-channel and P-channel MOSFETs generally include a polysilicon gate structure disposed between a drain and a source. The polysilicon gate structure controls charge carriers in a channel region to turn the transistor on and off.
According to conventional designs, threshold voltages for transistors on a single IC are variable by selectively providing channel implants for the transistors. Additional channel implants (e.g., doping the channel region to change the work function difference between the gate and the channel) are used for those transistors with higher threshold voltage requirements (e.g., Vth>0.3V). The transistors which have lower threshold voltage requirements (e.g., Vth≦0.3V) do not receive the additional channel implants.
Utilizing channel implants to adjust the threshold voltages of transistors can be problematic because transistor short-channel performance is very susceptible to process variations. In particular, short-channel performance is extremely sensitive to channel implants or additional doping steps. Accordingly, the modification of the channel with implants can result in significantly different short-channel performance between transistors, which adversely affects the predictability of the design and operability of the IC. This characteristic is particularly problematic as transistors become smaller and packing densities increase. Additionally, providing channel implants adds additional steps to the fabrication process and makes the IC more difficult to manufacture.
Polysilicon/germanium gate conductors are discussed in the above-referenced U.S. patent application Ser. Nos. 09/187,881, 09/187,842, 09/187,618, and 09/187,171. Transistors which utilize polysilicon/germanium gate conductors have significant advantages. The germanium concentration in the gate conductor can be used to adjust the gate work function. Controlling a variable gate work function allows threshold voltages to be adjusted by changing the germanium mole fraction in the gate conductor. This architecture avoids the limitations associated with conventional CMOS processes. Thus, this architecture, which does not rely on changing the channel doping concentration, provides a degree of design freedom over conventional approaches because concerns related to adverse effects on short-channel effects, immunity, channel carrier mobility, and others are reduced.
Further, polysilicon/germanium gate conductors have higher dopant activation rates, as compared with polysilicon gate conductors at the same temperature, and have a greater capability to suppress boron diffusion through thin gate oxides. Higher dopant activation rates allow lower thermal budgets to be utilized in the semiconductor fabrication process. Higher dopant activation rates can also reduce gate sheet resistance and gate depletion effect, which often degrade transistor performance. Boron penetration through the gate oxide can also degrade transistor performance.
In conventional CMOS processes, poor seeding of a polysilicon/germanium film due to large grain size can result when the polysilicon/germanium film is directly deposited on the top surface of the gate oxide. The poor seeding results in a rough surface that can degrade thickness uniformity across the wafer. Additionally, germanium in the gate conductor can be susceptible to outdiffusion away from the gate-oxide interface during high-temperature annealing. Loss of germanium from the gate-oxide interface can cause transistor performance instability. Further still, outgassing/outdiffusion and oxidation of the germanium in the gate conductor can degrade transistor performance. High concentration of germanium can also adversely affect the quality of silicides that are used to connect local interconnects, contacts, and vias.
Thus, there is a need for an integrated circuit or an electronic device that includes transistors having different threshold voltage levels which can be manufactured according to a simpler process. Further still, there is a need for a ULSI circuit that does not utilize channel implants to adjust threshold voltages among transistors. Even further still, there is a need for a process for fabricating transistors having gate stacks including germanium.
SUMMARY OF THE INVENTION
The present invention relates to a gate stack structure. The gate stack structure includes a gate insulating layer, a thin semiconductor seed layer disposed above the gate insulating layer, a semiconductor layer including germanium disposed above the thin semiconductor seed layer, and an amorphous semiconductor layer. The amorphous semiconductor layer is disposed above the semiconductor layer including germanium.
The present invention further relates to an integrated circuit including a plurality of transistors. The transistors include a gate dielectric, a seed layer disposed above the gate dielectric, and a compound semiconductor layer disposed above the seed layer. The compound semiconductor layer includes first semiconductor atoms and second semiconductor atoms.
The present invention even further still relates to a gate stack including a first type of semiconductor atoms and a second type of semiconductor atoms. The gate stack is manufactured by a method that includes providing a seed layer above a gate layer and providing a semiconductor layer. The semiconductor layer includes the first type of semiconductor atoms and the second type of semiconductor atoms. The semiconductor layer is disposed above the seed layer.
In accordance with an exemplary aspect of the present invention, a seed layer is provided before a polysilicon germanium layer is provided. The seed layer de
Adem Ercan
Yu Bin
Advanced Micro Devices , Inc.
Crane Sara
Foley & Lardner
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