Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-04-21
2002-04-30
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S355000, C257S367000, C257S488000, C326S080000, C326S093000
Reexamination Certificate
active
06380570
ABSTRACT:
DESCRIPTION
1. Field of the Invention
The present invention relates to semiconductor structures and, more particular to gate overvoltage control networks that can be used in semiconductor structures to protect the various gated devices present therein from exhibiting overvoltage conditions which may lead to early electrostatic discharge (ESD) failures. In some cases, the gate overvoltage control network of the present invention may be used to protect gated devices from undergoing charged device model (CDM) ESD failures.
2. Background of the Invention
In semiconductor processing, SOI (silicon-on-insulator) technology is becoming increasingly important since it permits the formation of high-speed integrated circuits. In SOI technology, a relatively thin layer of semiconducting material, e.g., Si, overlays a layer of insulating material (buried oxide region). This relatively thin layer of semiconducting material is generally the area wherein active devices are formed in SOI devices. Devices formed on SOI offer many advantages over their bulk Si counterparts, including higher performance, absence of latch-up, higher packing density and low voltage applications.
Despite the advantages obtained using SOI technology, SOI circuits, like other electronic devices, are susceptible to electrostatic discharge (ESD), i.e., a surge in voltage (negative or positive) that occurs when large amount of current is applied in the circuit. Moreover, the handling of SOI devices themselves may lead to charging of the substrate.
To discharge electrostatic impulses, ESD protection schemes need a low voltage turn-on and a high current drive (the ability to generate or sink a large amount of current before a large amount of negative or positive voltage is developed). Traditional bulk overvoltage protection schemes, such as diodes, do not work well on SOI because of the presence of the relatively thin SOI buried oxide layer. That is, conventional diodes on SOI devices have small current drivability because the current is carried laterally (limited by the thickness of the semiconductor material).
One approach for protecting SOI circuitry from ESD is found in U.S. Pat. No. 4,989,057 to Lu. Lu discloses a gated diode, which could be used for ESD design. The gated diode disclosed in Lu consists of a floating-body SOI transistor, with the gate connected to a signal pad. Although the diode disclosed in Lu can provide some ESD protection, the disclosed diode does not allow for obtaining ideal diode characteristics. Some reasons preventing ideal diode characteristics with the diodes disclosed in Lu include: (1) alignment tolerance of the substrate causes large process-induced variations; and (2) the conventional diode structure may be a polysilicon diode, which receives extensions and halo implants (implants normally utilized in deep sub-micron MOSFETs) that degrade the ideal characteristics on SOI. Other ESD protection schemes for the front side of the SOI wafer are also known. Common to each is that the energy developed across prior art ESD protection schemes can be substantial. Thus, the heat generated by such ESD protection schemes must be dissipated by the relatively thin semiconducting layer. In cases wherein the heat becomes too excessive, destruction of the SOI circuit may occur.
Another problem with prior art ESD networks is that under some operating conditions the various gated devices in which the ESD networks are suppose to protect undergo overvoltage conditions which may lead to early ESD failures. This problem is not limited to SOI devices. Instead, it exists in bulk Si devices as well.
Another problem with prior art ESD protection schemes is that they do not adequately eliminate charged device model (CDM) failure mechanism. In receiver circuits in SOI technology, experimental work has shown that N-channel metal oxide semiconductor field effect transistors (MOSFETs) fail due to current flowing in from the V
dd
power supply through the gate of the MOSFET causing MOSFET failure.
To date, no adequate control network has been developed that can be used in semiconductor structures to prevent the various gated devices present therein from exhibiting the above mentioned problems. There is thus a great need for developing a control network that can substantially eliminate overvoltage and/or avoid CDM ESD failures in the various gated devices present in semiconductor structures.
SUMMARY OF THE INVENTION
In one aspect, the present invention provides an overvoltage control network that can be implemented in various semiconductor structures, including SOI devices and bulk Si devices, that contain at least one gated device therein.
In yet another aspect, the present invention provides an overvoltage control network that is capable of reducing overvoltage, electrical stress, tunneling current, ESD, and CDM failure mechanism in various semiconductor structures which include at least one gated device region therein.
In another aspect, the present invention provides an overvoltage control network that can be used with diodes such as polysilicon diodes; buried resistors; resistors; transistors such as MOSFET, PFETs and NFETs; or other gated devices in which an overvoltage condition may cause device failure.
These and other advantages are achieved in the present invention by providing an overvoltage control network that is coupled to the gate of a gated device region that is present in a semiconductor structure.
Specifically, the present invention provides a semiconductor structure which comprises: an anode of a first conductivity type; a cathode of a second conductivity type; a device region separating said anode and said cathode, said device region including at least a dielectric gate; and an overvoltage control network coupled to the dielectric gate of said device region, wherein said overvoltage control network substantially reduces electrical overstress of said dielectric gate in said device region.
The term “device region” is used herein to denote a gated device region in which a dielectric layer separates a gate conductor from active areas that are present in a semiconductor substrate (bulk Si, Ge, III/V semiconductor compounds such as InAs, SiGe, GaAs and SiGe, silicon-on-insulators (SOIs), layered semiconductors such as Si/SiGe). Examples of suitable gated devices that can be employed in the present invention include, but are not limited to: diodes, resistors, buried resistors, MOSFETs, NFETs, PFETs and other like gated devices.
The term “anode” is used herein to denote an electron-collecting region, i.e., electron deficient region, of a semiconductor structure. Examples of anode regions include, but are not limited to: drain regions, positive terminals of a power supply and output terminals of an integrated circuit.
The term “cathode” is used herein to denote an electron-donating region, i.e., electron rich region, of a semiconductor structure. Examples of cathode regions include, but are not limited to: source regions, negative terminals of a power supply, pad regions and input terminals of an integrated circuits.
The term “overvoltage control network” is used herein to denote any network that is capable of reducing electrical overstress that may exist in a gated device region of a semiconductor structure. The overvoltage control network used in the present invention must be capable of being directly coupled to a gate dielectric layer present in the gated device region. Examples of suitable overvoltage control networks that can be employed in the present invention include, but are not limited to: diodes, resistors, buried resistors, dividers, on-MOSFETs, MOSFET voltage dividers, dummy inverters, lubistors, and other like control networks that can reduce electrical overstress of said gated device region. Combinations of one or more of these overvoltage control networks are also contemplated in the present invention.
The overvoltage control network may be connected to various external power supplies as well as the anode and cathode mentioned above. The overvoltage control network can also be used in conjunct
Henkler Richard A.
International Business Machines - Corporation
Scully Scott Murphy & Presser
Wojciechowicz Edward
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