Gate overlapping LDD structure

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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Details

257387, 257401, 257412, H01L 2978

Patent

active

052763471

ABSTRACT:
A method is provided for forming a gate overlap LDD structure of an integrated circuit, and an integrated circuit formed according to the same. An oxide layer is formed over a substrate. A four layered gate electrode is formed in an inverse T shape. A first polysilicon layer is formed over the underlying oxide layer. A first conductive layer is formed over the first polysilicon layer. A second polysilicon layer is formed over the first conductive layer. A second conductive layer is then formed over the second polysilicon layer. The second conductive and polysilicon layers are etched to expose a portion of the underlying first conductive layer. Lightly doped drain regions are formed in the substrate adjacent to the second conductive and polysilicon layers. Sidewall oxide spacers are formed on the sides of the second conductive and polysilicon layers and on top of the first conductive layer. The first conductive and polysilicon layers are etched exposing a portion of the underlying oxide layer. Source/drain regions are formed in the substrate adjacent to the first conductive and polysilicon layers.

REFERENCES:
patent: 4354309 (1982-10-01), Gardiner et al.
patent: 4963504 (1990-10-01), Huang
patent: 4984042 (1991-01-01), Pfiester et al.
patent: 5023679 (1991-06-01), Shibata
patent: 5053849 (1991-10-01), Izawa et al.
patent: 5061647 (1991-10-01), Roth et al.
patent: 5091763 (1992-02-01), Sanchez
"A Novel Submicron LDD Transistor With Inverse-T Gate Structure", by Tiao-yuan Huang, et al, IEDM 1986, pp. 742-745.

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