Gate insulated field effect transistor and method of...

Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Field effect device in non-single crystal – or...

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S066000, C257S057000, C257S058000, C257S061000

Reexamination Certificate

active

06737676

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor device and a method of manufacturing the same and, more particularly to thin film gate insulated field effect transistors suitable for use in liquid crystal displays and a method of manufacturing the same.
2. Description of the Prior Art
There have been well known in the art active liquid crystal displays which are driven by thin film transistors (TFTs). The displays of this type comprise visual panels and peripheral circuits for driving the panel. The peripheral circuit is formed by attaching a single crystalline chip containing integrated circuits on a glass substrate by tab-bonding or COG (chip on glass). The visual panel comprises a plurality of pixels each being provided with a driving TFT. The TET is usually an N-channel FET formed within an amorphous or polycrystalline semiconductor film which is electrically coupled to a respective pixel.
The carrier mobility in amorphous semiconductors, however, is substantially low, particularly the hole mobility is of the order of 0.1 cm
2
/Vsec or less. The drain dielectric strength of polycrystalline semiconductors, on the other hand, can not be sufficiently improved because of dangling bonds and impurities such as oxygen collected at grain boundaries, so that it is very difficult to realize usable P-channel TFTs having sufficient characteristics. Furthermore, such TFTs possess photosensitivities, which change Vg-ID characteristics in response to irradiation. Because of this, when used in displays accompanied by back-lights which light up the visual areas, e.g. at 2000 cd, the channel regions of the TFTs have to be covered by particular blind means.
FIG. 1
is a diagram illustrating the equivalent circuit of an exemplary liquid crystal display. The diagram shows only a 2×2 matrix for the sake of convenience in description whereas ordinary liquid crystal displays consist of more great numbers of pixels such as those in the form of a 640×480 matrix, a 1260×960 matrix and so on. The liquid crystal display includes a liquid crystal layer
42
a
disposed between a pair of glass substrates
11
and
11
′ as shown in FIG.
2
. Numeral
54
designates a polarizing plate. The inner surface of the substrate
11
′ is coated with a ground electrode
53
. The inner surface of the other substrate
11
is provided with a plurality of conductive pads each constituting one pixel of the display. Each conductive pad are formed together with an N-type FET
51
whose source is electrically connected with the corresponding pad. The drains of the FETs on a similar row in the matrix is connected with a control line of the row to which control signals are supplied from a row driver
47
. The gates of the N-type FETs on a similar column is connected with a control line of the column to which control signals are supplied from a column driver
46
.
In the operation of the display, the column driver
46
supplies control signals of a high level to selected columns to turn on the TFTs on the column. There are, however, undesirable cases in which the on-off action of the TFTs can not sufficiently carry out so that the output voltage of the TFT (i.e. the input to the pixel) reaches only short of a predetermined high voltage level (e.g. 5V), or the output voltage does not sufficiently fall to a predetermined low voltage (e.g. OV). The liquid crystal is intrinsically insulating and, when the TFT is turned off, the liquid crystal voltage (V
LC
) becomes floating. The amount of electric charge accumulated on the liquid crystal which is equivalent to a capacitance determines the V
LC
. The accumulated charge, however, will leak through a channel resistance R
LC
of the photosensitive TFT resulting in fluctuation of the V
LC
. Because of this, high efficiencies can not be expected when a large number of pixels are formed within one display panel.
BRIEF SUMMARY OF THE INVENTION
It is an object of the present invention to provide gate insulated field effect transistors and a manufacturing method for the transistors which are suitable for use in control circuits of optical devices.
It is another object of the present invention to provide gate insulated field effect transistors consisting of semiconductor films forming channel regions whose characteristics are little influenced by light rays incident thereupon.
Additional objects, advantages and novel features of the present invention will be set forth in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the present invention. The object and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
To achieve the foregoing and other object, and in accordance with the present invention, as embodied and broadly described herein, a semiconductor film to form a channel is formed on a substrate in order that the photosensitivity is substantially reduced by introduction of a spoiling agent such as oxygen, carbon, nitrogen or other suitable impurities. The channel is preferably formed within a non-single-crystalline semiconductor film such as semi-amorphous or semi-crsytalline semiconductor film. The drift of the output of the semiconductor transistor is then limited to a tolerable degree even when irradiated with light as bright as 2000 cd. In typical examples, the impurity is introduced into the semiconductor film at a total density of 1×10
20
cm
−3
to 8×10
21
cm
−3
(20 atom %), preferably 2×10
20
cm
−3
to 5×10
20
cm
−3
(2 atom %). The carrier mobility of the semiconductor film, however, can be improved to 5 cm
2
/Vsec by thermal treatment at 500° C. to 700° C. to make substantially ineffective the grain boundaries forming barrier against carrier transportation in the semiconductor film in virtue of recrystallization. Accordingly, the deviation of drain current is limited to 10% (on state) or less and two or less order of magnitude (off state), e.g. 10
−9
A (dark current) L10
−7
A (current under 2000 cd).
In typical example, the transistors according to the present invention are applied to liquid crystal displays. The transistors are preferably formed in a complimentary fashion. Each pixel of the display is provided with a switching element of complimentary thin film field effect transistors which forcibly pull or push the level of the liquid crystal layer to a definite high or low voltage level rather than a floating state. Of course, the present invention can be applied to a variety of other type transistors such as staggered types, coplanner types, inverted staggered types, inverted coplanner types. When control transistors of a driver for supplying control signals to the switching transistors are formed also on the same substrate at its peripheral position where no light is incident, they are not spoiled by the impurity. In such a case, two types of transistors are formed on the substrate, one being spoiled and the other not being spoiled and having a carrier mobility 2 to 4 times larger than that of the spoiled transistors.


REFERENCES:
patent: 2819191 (1958-07-01), Fuller
patent: 4068020 (1978-01-01), Reuschel
patent: 4103297 (1978-07-01), McGreivy et al.
patent: 4239346 (1980-12-01), Lloyd
patent: 4363828 (1982-12-01), Brodsky et al.
patent: 4365013 (1982-12-01), Ishioka et al.
patent: 4378417 (1983-03-01), Maruyama et al.
patent: 4395726 (1983-07-01), Maeguchi
patent: 4460670 (1984-07-01), Ogawa et al.
patent: 4470060 (1984-09-01), Yamazaki
patent: 4500388 (1985-02-01), Ohmura et al.
patent: 4565584 (1986-01-01), Tamura et al.
patent: 4581476 (1986-04-01), Yamazaki
patent: 4581620 (1986-04-01), Yamazaki et al.
patent: 4584025 (1986-04-01), Takaoka et al.
patent: 4591892 (1986-05-01), Yamazaki
patent: 4597160 (1986-07-01), Ipri
patent: 4621276 (1986-11-01), Malhi
patent: 4648691 (1987-03-01), Oguchi et al.
patent: 46

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Gate insulated field effect transistor and method of... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Gate insulated field effect transistor and method of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Gate insulated field effect transistor and method of... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3189712

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.