Gate-induced strain for MOS performance improvement

Details Gate-induced strain for MOS performance improvement Gate-induced strain for MOS performance improvement

2006-01-03

2006-01-03

Pham, Hoai (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Thin active physical layer which is

Heterojunction

C257S020000, C257S190000

Reexamination Certificate

active

06982433

ABSTRACT:
There is disclosed an apparatus including a substrate defining an interior of the apparatus, a device exterior to the substrate including a gate electrode, and a straining layer exterior to the gate electrode and exterior to the substrate.

REFERENCES:
patent: 5906708 (1999-05-01), Robinson et al.
patent: 5963817 (1999-10-01), Chu et al.
patent: 6242327 (2001-06-01), Yokoyama et al.
patent: 6335233 (2002-01-01), Cho et al.
patent: 6365472 (2002-04-01), Ishimaru et al.
patent: 6395621 (2002-05-01), Mizushima et al.
patent: 6455364 (2002-09-01), Asai et al.
patent: 6455871 (2002-09-01), Shim et al.
patent: 6465283 (2002-10-01), Chang et al.
patent: 6492216 (2002-12-01), Yeo et al.
patent: 2002/0052084 (2002-05-01), Fitzgerald
patent: 2002/0081861 (2002-06-01), Robinson et al.
patent: 2002/0086503 (2002-07-01), Schuegraf et al.
patent: 2002/0140031 (2002-10-01), Rim
patent: 2004/0075148 (2004-04-01), Kumagai et al.
patent: 07202178 (1993-12-01), None
PCT Notification of Trasmittal of the International Search Report and the Written Opinion of the International Search Authority, or the Declaration, Oct. 26, 2004.
Ota, K., et al., “Novel locally strained channel technique for high performance 55nm CMOS,” International Electron Devices Meeting, 2002, pp. 27-30.

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