Gate ground circuit approach for I/O ESD protection

Details Gate ground circuit approach for I/O ESD protection Gate ground circuit approach for I/O ESD protection

2001-09-27

2002-07-02

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

C327S314000, C327S325000

Reexamination Certificate

active

06414532

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to the protection of integrated circuits from electrostatic discharge (ESD), and more particularly to the method of providing substrate current flow in an NMOS cascode circuit in an ESD event.
2. Description of the Related Art
In the present conventional 5VT Input/Output (I/O) circuit structure for ESD protection where two NMOS cascode circuits are used, the protection from ESD is diminished because current flow, caused by an ESD, is impeded in the NMOS cascode circuits. While the first NMOS transistor of each NMOS cascode circuit is on—caused by the coupling up of an ESD pulse into its gate—the second NMOS transistor of the second NMOS cascode circuit is off. The resulting current non-uniformity between the NMOS cascode circuits causes the device to fail at low ESD zapping voltages.
FIG. 1
is a depiction of such a circuit of the prior art which will be described next.
Circuit
10
of
FIG. 1
comprises at least one driver circuit
2
, ESD protection circuit
3
, and Vcc/Vss protection circuit
4
. Driver circuit
2
has input
6
which couples to the gate of PMOS transistor
200
, and input
7
which couples to the gate of NMOS transistor
220
. Connected in series between voltage supply
8
and reference potential
9
(typically ground) are PMOS transistor
220
, and NMOS transistors
210
and
220
. The gate of transistor
210
is coupled to voltage supply
8
, and the junction J
1
of transistors
200
and
210
is connected to I/O pad
32
. ESD protection circuit
3
comprises, in series between voltage supply
8
and reference potential
9
, PMOS transistor
300
, and NMOS transistors
310
and
320
, respectively. The gates of transistors
300
and
310
are coupled to voltage supply
8
, and the gate of transistor
320
is coupled to reference potential
9
. The junction J
2
between transistors
300
and
310
is coupled to I/O pad
32
. Vcc/Vss protection circuit
4
is coupled in series between voltage supply
8
and reference potential
9
. Typically Vcc/Vss protection circuit
4
comprises a plurality of NMOS transistors
400
and resistive means
410
, where the latter are coupled between the gates of NMOS transistors
400
and reference potential
9
. The drains and sources of transistors
400
are coupled to voltage supply
8
and reference potential
9
, respectively.
Referring now to
FIG. 1
,
FIG. 2
a
, and
FIG. 2
b
, we continue with the description of the prior art circuit. NMOS transistors
210
and
220
form a cascode circuit
20
where the source
212
of transistor
210
and the drain
221
of transistor
220
share a diffusion region
21
. Similarly, NMOS transistors
310
and
320
form a cascode circuit
30
where the source
312
of transistor
310
and the drain
321
of transistor
320
share a diffusion region
31
. NMOS transistor
210
and NMOS transistor
310
are customarily called the “first transistor” or “N
1
” of each cascode circuit, and transistors
220
and
320
are called the “second transistor” or “N
2
.”
The problem with the circuit of
FIG. 1
is that the voltage at the gate of NMOS transistors
210
,
220
and
310
will be coupled up by an ESD pulse because these gates are in effect floating with respect to an ESD (when transistor
400
is off then the gates of transistors
210
and
310
are in effect floating, therefore, the gate voltage of transistors
210
and
310
will be coupled up by the drain voltage of
210
and
310
, respectively). Therefore, the ESD pulse will travel at the surface of NMOS transistors
210
and
220
(in the n-channel). In the second cascode circuit, the gate of NMOS transistor
320
is connected to ground and, therefore, off (no n-channel) during an ESD while transistor
310
is on. Thus, the ESD pulse cannot travel at the surface of NMOS transistors
310
and
320
. Hence, ESD protection will fail at low ESD voltages because of the current non-uniformity between driver circuit
2
and ESD protect circuit
3
.
Prior art U.S. Patents which relate to the subject of ESD protection are:
U.S. Pat. No. 5,572,394 (Ker et al.) CMOS On-Chip Four-LVTSCR ESD Protection Scheme.
U.S. Pat. No. 5,804,861 (Leach) Electrostatic Discharge Protection in Integrated Circuits, Systems and Methods.
U.S. Pat. No. 5,852,375 (Byrne et al.) 5V Tolerant I/O Circuit.
U.S. Pat. No. 67005,413 (Schmitt) 5V Tolerant PCI I/O Buffer on 2.5′V Technology.
U.S. Pat. No. 6,028,450 (Nance) Programmable Input/Output Circuit with Pull-Up Bias Control.
U.S. Pat. No. 6,049,119 (Smith) Protection Circuit for a Semiconductor Device.
U.S. Pat. No. 67097,071 (Krakauer) ESD Protection Clamp for Mixed Voltage I/O Stages Using NMOS Transistors.
While above U.S. Patents offer various circuits and methods of protecting devices from destructive ESD, none of them use a clamping circuit to pull down to ground (reference potential) the first poly gate of each cascode circuit. The proposed circuit improves the ESD performance and eliminates the non-uniform current distribution in the cascode circuits of the prior art.
SUMMARY OF THE INVENTION
It is an object of the present invention to improve the ESD performance of the I/O ESD protection circuit.
It is another object of the present invention to create a uniform current flow between the first and the second NMOS cascode circuit.
It is yet another object of the present invention to force the gates of the first NMOS transistors to near ground (reference potential).
It is still another object of the present invention to improve the ESD performance with a minimal change to the I/O ESD protection circuit.
These and many other objects have been achieved by providing the I/O ESD protection circuit with driver circuits, ESD protection circuits, a Vcc/Vss protection circuit with a plurality of NMOS transistors, and by adding clamping circuits between the I/O pad of the ESD protection circuit and the Vcc/Vss protection circuit. Clamping circuits are implemented typically by a diode which has its cathode coupled to the I/O pad. NMOS cascode circuits of each driver circuit and each ESD protection circuit react to an ESD by having their first poly gates pulled down to ground by each clamping circuit. This clamping action prevents the gate voltage of the first NMOS transistor of the NMOS cascode circuits to be coupled up by an ESD pulse. This clamping action creates a current flow from the drain of the first NMOS transistor through the P-well to the source of the second NMOS transistor of each of the NMOS cascode circuits and, thus, prevents device failure at low ESD voltages. The current flow through the P-well is made possible by the action of a parasitic bipolar npn transistor which is created by the N+ drain (collector) of the first NMOS transistor, the P-well (base), and the N+ source (emitter) of the second NMOS transistor of both NMOS cascode circuits. The parasitic bipolar npn transistor is created when the poly gate of the first transistor is clamped to ground.
These and many other objects and advantages of the present invention will be readily apparent to one skilled in the art to which the invention pertains from a perusal of the claims, the appended drawings, and the following detailed description of the preferred embodiments.


REFERENCES:
patent: 5572394 (1996-11-01), Ker et al.
patent: 5804861 (1998-09-01), Leach
patent: 5831466 (1998-11-01), Pulvirenti et al.
patent: 5852375 (1998-12-01), Byrne et al.
patent: 6005413 (1999-12-01), Schmitt
patent: 6008974 (1999-12-01), Lee et al.
patent: 6028450 (2000-02-01), Nance
patent: 6049119 (2000-04-01), Smith
patent: 6097071 (2000-08-01), Krakauer
patent: 6271999 (2001-08-01), Lee et al.

Affiliated with

Also associated with

Rating

Gate ground circuit approach for I/O ESD protection does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Gate ground circuit approach for I/O ESD protection, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Gate ground circuit approach for I/O ESD protection will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2823854