Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
2000-08-17
2002-11-19
Fahmy, Wael (Department: 2823)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S459000, C438S585000
Reexamination Certificate
active
06482725
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of manufacturing semiconductor devices, e.g., MOS and CMOS transistors and integrated circuits containing such transistors on a common semiconductor substrate, with improved processing methodology resulting in increased reliability, quality, and device performance. The present invention has particular applicability in fabricating high-density integration semiconductor devices with design features below about 0.18 &mgr;m, e.g., about 0.15 &mgr;m and below.
BACKGROUND OF THE INVENTION
The escalating requirements for high density and performance associated with ultra-large-scale integration (ULSI) semiconductor devices require design features of
0
.
18
&mgr;m and below, such as 0.15&mgr;m and below, increased transistor and circuit speeds, high reliability, and increased manufacturing throughput and product yield for economic competitiveness. The reduction of design features to 0.18 &mgr;m and below challenges the limitations of conventional semiconductor manufacturing techniques.
A conventional approach for forming active devices, such as MOS and/or CMOS transistors in or on a semiconductor substrate, involves formation of a thin gate oxide layer on the active areas of a cleaned surface of the semiconductor substrate, e.g., an about 25-50 Å thick silicon oxide layer in the case of silicon-based devices, followed by blanket deposition thereon of a gate material comprising a relatively thin layer of polysilicon. Inasmuch as the quality of the gate oxide is critical for good device performance, great care is taken during and between these steps to prevent contamination of the gate oxide. For example, the oxidation step for forming the gate oxide layer is typically performed in dedicated furnace tubes, and a direct transfer from gate oxidation to poly deposition is utilized in order to minimize exposure of unprotected gate oxide. A gate mask is then employed for defining the gate area(s) in resist and the polysilicon layer is etched away from the other areas.
In subsequent ion implantation processing to form lightly- or moderately-doped source/drain extension implants in the semiconductor substrate, the implantation energies are carefully selected to be low enough to prevent penetration of the gate oxide by implanted dopant ions. Similarly, the implantation energies of e.g., arsenic and boron difluoride ions employed during formation of moderately- to heavily-doped source/drain implants are selected as to be low enough to form shallow junction n-channel and p-channel S/D regions in the substrate while doping the polysilicon gate areas to relatively good conductivities with minimal dopant penetration/diffusion into the underlying gate oxide. Dopant depletion the gate polysilicon disadvantageously reduces the conductivity thereof, whereas dopant penetration and contamination of the gate oxide layer adversely results in a reduction of the insulative properties thereof. In addition, such boron penetration of the gate oxide degrades MOS transistor properties such as, for example, threshold voltage V
T
.
However, such standard precautions as described above are generally insufficient for adequately minimizing or preventing deleterious dopant depletion of the polysilicon gate layer and resultant dopant penetration of the underlying gate oxide layer. This is particularly problematic in the case of boron-containing p-type dopants, principally due to the ease with which boron ions or atoms diffuse in silicon substrates. Boron depletion from p
+
gate polysilicon layers with attendant gate oxide penetration is of special concern when subsequent device processing includes post-implantation annealing, e.g., RTA, for dopant activation and lattice damage relaxation. For example, it has been reported that boron will penetrate gate oxides of about 12.6 nm or less thick during a 900° C. 30 minute post-implant anneal in nitrogen. Such boron penetration results in a positive shift in the threshold voltage V
T
of implanted PMOS transistors. In some instances, boron penetration will continue into underlying silicon. It has also been determined that the presence of fluorine in the gate oxide exacerbates the boron penetration problem. Such boron penetration of the gate oxide can readily occur if the PMOS source/drain regions are implanted with BF
2
ion species. As a consequence, implantation of elemental boron ions is considered inherently superior to BF
2
implantation for surface-channel PMOS devices in CMOS technologies utilizing p-doped polysilicon gates.
Accordingly, there exists a need for improved semiconductor methodology for fabrication of MOS and/or CMOS transistors and integrated circuit devices comprising a plurality of such devices which does not suffer from the above-described drawbacks associated with the conventional methodology. There exists a need for an improved process for fabricating MOS and/or CMOS transistors which minimizes or substantially eliminates deleterious dopant depletion of the gate polysilicon and associated dopant penetration of the gate oxide, and which provides a significant improvement in transistor threshold voltage stability, and device quality and performance.
DISCLOSURE OF THE INVENTION
An advantage of the present invention is an improved method for fabricating semiconductor devices utilizing gate oxide and polysilicon gate layers wherein dopant depletion of the gate polysilicon layers and resultant dopant penetration of underlying gate oxide layers are minimized or substantially eliminated.
Another advantage of the present invention is an improved method for fabricating a MOS or CMOS transistor device comprising eliminating or substantially reducing depletion of boron p-type dopant from a gate polysilicon layer and its attendant penetration of an underlying gate oxide layer.
Still another advantage of the present invention is an improved silicon-based MOS or CMOS transistor device comprising a polysilicon gate having a reduced amount of boron depletion therefrom and an underlying silicon oxide gate insulator layer having reduced boron penetration thereinto.
Additional advantages and other features of the present invention will be set forth in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the instant invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to an aspect of the present invention, the foregoing and other advantages are achieved in part by a method of fabricating a semiconductor device comprising a thin gate insulating layer and an overlying electrically conductive gate layer, which method comprises the sequential steps of:
(a) providing a first, heavily-doped, p
+
or n
+
type semiconductor substrate of predetermined thickness and having opposed, spaced-apart, first and second major surfaces with a plurality of side surfaces therebetween;
(b) forming a thin gate insulating layer on the first major surface of the first substrate;
(c) implanting impurities into the exposed surface of the gate insulating layer, the impurities passing through the gate insulating layer and penetrating the underlying first semiconductor substrate for a predetermined depth below the first major surface, the structural integrity of the first substrate being weakened at the predetermined depth;
(d) cleaving the implanted first substrate along a cleavage plane parallel to the first major surface and located at the predetermined depth;
(e) providing a second semiconductor substrate of same conductivity type as the first semiconductor substrate, the second substrate having opposed, spaced-apart first and second major surfaces; and
(f) bonding the exposed surface of the gate insulating insulating layer of the cleaved first substrate to the first major surface of the second substrate; whereby the first, heavily-doped semiconductor substrate forms an electrically conductive gate
Advanced Micro Devices , Inc.
Fahmy Wael
Garcia Joannie Adelle
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