Gate electrode stress control for finFET performance...

Details Gate electrode stress control for finFET performance... Gate electrode stress control for finFET performance...

2005-11-03

2010-02-02

Wojciechowicz, Edward (Department: 2895)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S198000, C257S064000, C257S347000, C257S401000, C257S521000, C257S527000, C257S627000, C257S628000

Reexamination Certificate

active

07655511

ABSTRACT:
A finFET and its method for fabrication include a gate electrode formed over a channel region of a semiconductor fin. The semiconductor fin has a crystallographic orientation and an axially specific piezoresistance coefficient. The gate electrode is formed with an intrinsic stress determined to influence, and preferably optimize, charge carrier mobility within the channel region. To that end, the intrinsic stress preferably provides induced axial stresses within the gate electrode and semiconductor fin channel region that complement the axially specific piezoresistance coefficient.

REFERENCES:
patent: 3602841 (1971-08-01), McGroddy
patent: 4665415 (1987-05-01), Esaki et al.
patent: 4853076 (1989-08-01), Tsaur et al.
patent: 4855245 (1989-08-01), Neppl et al.
patent: 4952524 (1990-08-01), Lee et al.
patent: 4958213 (1990-09-01), Eklund et al.
patent: 5006913 (1991-04-01), Sugahara et al.
patent: 5060030 (1991-10-01), Hoke
patent: 5081513 (1992-01-01), Jackson et al.
patent: 5108843 (1992-04-01), Ohtaka et al.
patent: 5134085 (1992-07-01), Gilgen et al.
patent: 5310446 (1994-05-01), Konishi et al.
patent: 5354695 (1994-10-01), Leedy
patent: 5371399 (1994-12-01), Burroughes et al.
patent: 5391510 (1995-02-01), Hsu et al.
patent: 5459346 (1995-10-01), Asakawa et al.
patent: 5471948 (1995-12-01), Burroughes et al.
patent: 5557122 (1996-09-01), Shrivastava et al.
patent: 5561302 (1996-10-01), Candelaria
patent: 5565697 (1996-10-01), Asakawa et al.
patent: 5571741 (1996-11-01), Leedy et al.
patent: 5592007 (1997-01-01), Leedy
patent: 5592018 (1997-01-01), Leedy
patent: 5670798 (1997-09-01), Schetzina
patent: 5679965 (1997-10-01), Schetzina
patent: 5683934 (1997-11-01), Candelaria
patent: 5840593 (1998-11-01), Leedy
patent: 5861651 (1999-01-01), Brasen et al.
patent: 5880040 (1999-03-01), Sun et al.
patent: 5940736 (1999-08-01), Brady et al.
patent: 5946559 (1999-08-01), Leedy
patent: 5960297 (1999-09-01), Saki
patent: 5989978 (1999-11-01), Peidous
patent: 6008126 (1999-12-01), Leedy
patent: 6025280 (2000-02-01), Brady et al.
patent: 6046464 (2000-04-01), Schetzina
patent: 6066545 (2000-05-01), Doshi et al.
patent: 6090684 (2000-07-01), Ishitsuka et al.
patent: 6107143 (2000-08-01), Park et al.
patent: 6117722 (2000-09-01), Wuu et al.
patent: 6133071 (2000-10-01), Nagai
patent: 6165383 (2000-12-01), Chou
patent: 6221735 (2001-04-01), Manley et al.
patent: 6228694 (2001-05-01), Doyle et al.
patent: 6246095 (2001-06-01), Brady et al.
patent: 6255169 (2001-07-01), Li et al.
patent: 6261964 (2001-07-01), Wu et al.
patent: 6265317 (2001-07-01), Chiu et al.
patent: 6274444 (2001-08-01), Wang
patent: 6281532 (2001-08-01), Doyle et al.
patent: 6284623 (2001-09-01), Zhang et al.
patent: 6284626 (2001-09-01), Kim
patent: 6319794 (2001-11-01), Akatsu et al.
patent: 6326667 (2001-12-01), Sugiyama et al.
patent: 6361885 (2002-03-01), Chou
patent: 6362082 (2002-03-01), Doyle et al.
patent: 6368931 (2002-04-01), Kuhn et al.
patent: 6403486 (2002-06-01), Lou
patent: 6403975 (2002-06-01), Brunner et al.
patent: 6406973 (2002-06-01), Lee
patent: 6461936 (2002-10-01), Von Ehrenwall
patent: 6476462 (2002-11-01), Shimizu et al.
patent: 6479166 (2002-11-01), Heuer et al.
patent: 6493497 (2002-12-01), Ramdani et al.
patent: 6498358 (2002-12-01), Lach et al.
patent: 6501121 (2002-12-01), Yu et al.
patent: 6506652 (2003-01-01), Jan et al.
patent: 6509618 (2003-01-01), Jan et al.
patent: 6521964 (2003-02-01), Jan et al.
patent: 6531369 (2003-03-01), Ozkan et al.
patent: 6531740 (2003-03-01), Bosco et al.
patent: 6603156 (2003-08-01), Rim
patent: 6645826 (2003-11-01), Yamazaki et al.
patent: 6767802 (2004-07-01), Maa et al.
patent: 6774015 (2004-08-01), Cohen et al.
patent: 6815278 (2004-11-01), Ieong et al.
patent: 6815738 (2004-11-01), Rim
patent: 6828214 (2004-12-01), Notsu
patent: 6828628 (2004-12-01), Hergenrother et al.
patent: 6831292 (2004-12-01), Currie et al.
patent: 7115920 (2006-10-01), Bernstein et al.
patent: 2001/0009784 (2001-07-01), Ma et al.
patent: 2002/0074598 (2002-06-01), Doyle et al.
patent: 2002/0086472 (2002-07-01), Roberds et al.
patent: 2002/0086497 (2002-07-01), Kwok
patent: 2002/0090791 (2002-07-01), Doyle et al.
patent: 2003/0032261 (2003-02-01), Yeh et al.
patent: 2003/0040158 (2003-02-01), Saitoh
patent: 2003/0057184 (2003-03-01), Yu et al.
patent: 2003/0067035 (2003-04-01), Tews et al.
patent: 2005/0093067 (2005-05-01), Yeo et al.
patent: 2005/0130358 (2005-06-01), Chidambarrao et al.
patent: 2006/0177998 (2006-08-01), Lin et al.
patent: 2007/0132053 (2007-06-01), King et al.
patent: 1684271 (2005-10-01), None
patent: 01/162362 (1989-06-01), None
patent: 0 967 636 (1999-12-01), None
patent: 1 174 928 (2002-01-01), None
patent: WO 94/27317 (1993-05-01), None
patent: WO 02/45156 (2002-06-01), None
Rim, et al., “Transconductance Enhancement in Deep Submicron Strained-Sin-MOSFETs”, International Electron Devices Meeting, 26, 8, 1, IEEE, Sep. 1998.
Rim, et al. “Characteristics and Device Design of Sub-100 nm Strained Si N- and PMOSFETs”, 2002 Symposium on VLSI Technology Digest of Technical Papers, IEEE, pp. 98-99.
Scott, et al. “NMOS Drive Current Reduction Caused by Transistor Layout and Trench Isolation Induced Stress”, International Electron Devices Meeting, 34.4.1, IEEE, Sep. 1999.
Ootsuka, et al. “A Highly Dense, High-Performance 130nm node CMOS Technology for Large Scale System-on-a-Chip Application”, International Electron Device Meeting, 23.5.1, IEEE, Apr. 2000.
Ito, et al. “Mechanical Stress Effect of Etch-Stop Nitride and its Impact on Deep Submicron Transistor Design”, International Electron Devices Meeting, 10.7.1, IEEE, Apr. 2000.
Shimizu, et al. “Local Mechanical-Stress Control (LMC): A New Technique for CMOS-Performance Enhancement”, International Electron Devices Meeting, IEEE, Mar. 2001.
Ota, et al. “Novel Locally Strained Channel Technique for high Performance 55nm CMOS”, International Electron Devices Meeting, 2.2.1, IEEE, Feb. 2002.
Ouyang, et al. “Two-Dimensional Bandgap Engineering in a Novel Si/SiGe pMOSFETS With Enhanced Device Performance and Scalability”, Microelectronics Research Center, pp. 151-154, 2000 IEEE.
Sayama et al., “Effect of <Channel Direction for High Performance SCE Immune pMOSFET with Less Than 0.15um Gate Length”ULSI Development Center, pp. 27.5.1-27.5.4, 1999 IEEE.
Yin, et al., “Fully-depleted Strained-Si on Insulator NMOSFETs without Relaxed SiGe Buffers”, IEDM, 2003 IEEE.
Yin, et al., “Strain partition of Si/SiGe and SiO2/SiGe on compliant substrates”, Applied Physics Letters, vol. 82, No. 22, Jun. 2, 2003, pp. 3853-3855.
Huang, et al., “Relaxation of a Strained Elastic Film on a Viscous Layer”, Mat. Res. Soc. Symp. Proc., vol. 695, 2002 Materials Research Society; pp. L3.14.1-L3.14.6.
Yin, et al., “Strain relaxation of SiGe islands on compliant oxide”, Journal of Applied Physics, vol. 91, No. 12, Jun. 15, 2002, pp. 9716-9722.
“AmberWave and Aixtron to develop CVD equipment for SiGe and strained Si”, http://www.compoundsemiconductor.net/articles
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