Gate electrode stress control for finFET performance...

Details Gate electrode stress control for finFET performance... Gate electrode stress control for finFET performance...

2011-06-14

2011-06-14

Wojciechowicz, Edward (Department: 2895)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S064000, C257S288000, C257S347000, C257S351000, C257S402000, C257S412000, C257S521000, C257S527000, C257S627000, C257S628000

Reexamination Certificate

active

07960801

ABSTRACT:
A finFET and its method for fabrication include a gate electrode formed over a channel region of a semiconductor fin. The semiconductor fin has a crystallographic orientation and an axially specific piezoresistance coefficient. The gate electrode is formed with an intrinsic stress determined to influence, and preferably optimize, charge carrier mobility within the channel region. To that end, the intrinsic stress preferably provides induced axial stresses within the gate electrode and semiconductor fin channel region that complement the axially specific piezoresistance coefficient.

REFERENCES:
patent: 3602841 (1971-08-01), McGroddy
patent: 4665415 (1987-05-01), Esaki et al.
patent: 4853076 (1989-08-01), Tsaur et al.
patent: 4855245 (1989-08-01), Neppl et al.
patent: 4952524 (1990-08-01), Lee et al.
patent: 4958213 (1990-09-01), Eklund et al.
patent: 4969023 (1990-11-01), Svedberg
patent: 5006913 (1991-04-01), Sugahara et al.
patent: 5060030 (1991-10-01), Hoke et al.
patent: 5081513 (1992-01-01), Jackson et al.
patent: 5108843 (1992-04-01), Ohtaka et al.
patent: 5134085 (1992-07-01), Gilgen et al.
patent: 5268330 (1993-12-01), Givens et al.
patent: 5310446 (1994-05-01), Konishi et al.
patent: 5354695 (1994-10-01), Leedy
patent: 5371399 (1994-12-01), Burroughes et al.
patent: 5391510 (1995-02-01), Hsu et al.
patent: 5459346 (1995-10-01), Asakawa et al.
patent: 5471948 (1995-12-01), Burroughes et al.
patent: 5557122 (1996-09-01), Shrivastava et al.
patent: 5561302 (1996-10-01), Candelaria
patent: 5565697 (1996-10-01), Asakawa et al.
patent: 5571741 (1996-11-01), Leedy
patent: 5583369 (1996-12-01), Yamazaki et al.
patent: 5592007 (1997-01-01), Leedy
patent: 5592009 (1997-01-01), Hideka
patent: 5592018 (1997-01-01), Leedy
patent: 5670798 (1997-09-01), Schetzina
patent: 5679965 (1997-10-01), Schetzina
patent: 5683934 (1997-11-01), Candelaria
patent: 5698869 (1997-12-01), Yoshimi et al.
patent: 5840593 (1998-11-01), Leedy
patent: 5841170 (1998-11-01), Adan et al.
patent: 5861651 (1999-01-01), Brasen et al.
patent: 5880040 (1999-03-01), Sun et al.
patent: 5940716 (1999-08-01), Jin et al.
patent: 5940736 (1999-08-01), Brady et al.
patent: 5946559 (1999-08-01), Leedy
patent: 5960297 (1999-09-01), Saki
patent: 5989978 (1999-11-01), Peidous
patent: 6008126 (1999-12-01), Leedy
patent: 6025280 (2000-02-01), Brady et al.
patent: 6046464 (2000-04-01), Schetzina
patent: 6066545 (2000-05-01), Doshi et al.
patent: 6090684 (2000-07-01), Ishitsuka et al.
patent: 6107143 (2000-08-01), Park et al.
patent: 6117722 (2000-09-01), Wuu et al.
patent: 6133071 (2000-10-01), Nagai
patent: 6165383 (2000-12-01), Chou
patent: 6221735 (2001-04-01), Manley et al.
patent: 6228694 (2001-05-01), Doyle et al.
patent: 6246095 (2001-06-01), Brady et al.
patent: 6255169 (2001-07-01), Li et al.
patent: 6255695 (2001-07-01), Kubota et al.
patent: 6261964 (2001-07-01), Wu et al.
patent: 6265317 (2001-07-01), Chiu et al.
patent: 6274444 (2001-08-01), Wang
patent: 6281532 (2001-08-01), Doyle et al.
patent: 6284623 (2001-09-01), Zhang et al.
patent: 6284626 (2001-09-01), Kim
patent: 6319794 (2001-11-01), Akatsu et al.
patent: 6361885 (2002-03-01), Chou
patent: 6362082 (2002-03-01), Doyle et al.
patent: 6368931 (2002-04-01), Kuhn et al.
patent: 6403486 (2002-06-01), Lou
patent: 6403975 (2002-06-01), Brunner et al.
patent: 6406973 (2002-06-01), Lee
patent: 6461936 (2002-10-01), von Ehrenwall
patent: 6468872 (2002-10-01), Yang
patent: 6476462 (2002-11-01), Shimizu et al.
patent: 6483171 (2002-11-01), Forbes et al.
patent: 6493497 (2002-12-01), Ramdani et al.
patent: 6498358 (2002-12-01), Lach et al.
patent: 6501121 (2002-12-01), Yu et al.
patent: 6506652 (2003-01-01), Jan et al.
patent: 6509618 (2003-01-01), Jan et al.
patent: 6521964 (2003-02-01), Jan et al.
patent: 6531369 (2003-03-01), Ozkan et al.
patent: 6531740 (2003-03-01), Bosco et al.
patent: 6605498 (2003-08-01), Murthy et al.
patent: 6621131 (2003-09-01), Murthy et al.
patent: 6621392 (2003-09-01), Volant et al.
patent: 6635506 (2003-10-01), Volant et al.
patent: 6717216 (2004-04-01), Doris et al.
patent: 6806584 (2004-10-01), Fung et al.
patent: 6815278 (2004-11-01), Ieong et al.
patent: 6825529 (2004-11-01), Chidambarrao et al.
patent: 6831292 (2004-12-01), Currie et al.
patent: 6869866 (2005-03-01), Chidambarrao et al.
patent: 6890808 (2005-05-01), Chidambarrao et al.
patent: 6930030 (2005-08-01), Rausch et al.
patent: 6964892 (2005-11-01), Clevenger et al.
patent: 6974981 (2005-12-01), Chidambarrao et al.
patent: 6977194 (2005-12-01), Belyansky et al.
patent: 6998657 (2006-02-01), Rhodes
patent: 7015082 (2006-03-01), Doris et al.
patent: 7268024 (2007-09-01), Yeo et al.
patent: 7528465 (2009-05-01), King et al.
patent: 2001/0009784 (2001-07-01), Ma et al.
patent: 2002/0063292 (2002-05-01), Armstrong et al.
patent: 2002/0074598 (2002-06-01), Doyle et al.
patent: 2002/0086472 (2002-07-01), Roberds et al.
patent: 2002/0086497 (2002-07-01), Kwok
patent: 2002/0090791 (2002-07-01), Doyle et al.
patent: 2003/0032261 (2003-02-01), Yeh et al.
patent: 2003/0040158 (2003-02-01), Saitoh
patent: 2003/0057184 (2003-03-01), Yu et al.
patent: 2003/0067035 (2003-04-01), Tews et al.
patent: 2003/0129791 (2003-07-01), Yamazaki
patent: 2003/0181005 (2003-09-01), Hachimine et al.
patent: 2004/0029323 (2004-02-01), Shimizu et al.
patent: 2004/0051144 (2004-03-01), Webb et al.
patent: 2004/0113174 (2004-06-01), Chidambarrao et al.
patent: 2004/0113217 (2004-06-01), Chidambarrao et al.
patent: 2004/0173815 (2004-09-01), Yeo et al.
patent: 2004/0238914 (2004-12-01), Deshpande et al.
patent: 2004/0262784 (2004-12-01), Doris et al.
patent: 2005/0017304 (2005-01-01), Matsushita
patent: 2005/0040460 (2005-02-01), Chidambarrao et al.
patent: 2005/0082634 (2005-04-01), Doris et al.
patent: 2005/0093030 (2005-05-01), Doris et al.
patent: 2005/0098234 (2005-05-01), Nakaharai et al.
patent: 2005/0098829 (2005-05-01), Doris et al.
patent: 2005/0106799 (2005-05-01), Doris et al.
patent: 2005/0139929 (2005-06-01), Rost
patent: 2005/0145954 (2005-07-01), Zhu et al.
patent: 2005/0148146 (2005-07-01), Doris et al.
patent: 2005/0194699 (2005-09-01), Belyansky et al.
patent: 2005/0236668 (2005-10-01), Zhu et al.
patent: 2005/0245017 (2005-11-01), Belyansky et al.
patent: 2005/0280051 (2005-12-01), Chidambarrao et al.
patent: 2005/0282325 (2005-12-01), Belyansky et al.
patent: 2006/0022266 (2006-02-01), Messenger et al.
patent: 2006/0027868 (2006-02-01), Doris et al.
patent: 2006/0057787 (2006-03-01), Doris et al.
patent: 2006/0060925 (2006-03-01), Doris et al.
patent: 2006/0094212 (2006-05-01), Noguchi et al.
patent: 2006/0177998 (2006-08-01), Lin et al.
patent: 2006/0246641 (2006-11-01), Kammler et al.
patent: 2006/0284255 (2006-12-01), Shin et al.
patent: 1591826 (2005-03-01), None
patent: 6476755 (1989-03-01), None
Rim et al., “Transductance Enhancement in Deep Submicron Strained-Si n-MOSFETs”, International Electron Devices Meeting, IEEE, 1998, 26.8.1-26.8.4.
Rim et al., “Characteristics and Device Design of Sub-100 nm Strained Si N- and PMOSFETs”, Symposium on VLSI Technology Digest of Technical Papers, IEEE, 2002, pp. 98-99.
Scott et al., NMOS Drive Current Reduction Caused by Transistor Layout and Trench Isolation Induced Stress, International Electron Devices Meeting, IEEE, 1999, 34.4.1-34.4.4.
Ootsuka et al., “A Highly Dense, High-Performance 130nm Node CMOS Technology for Large Scale System-on-a-Chip Applications”, International Electron Devices Meeting, IEEE, 2000, 23.5.1-23.5.4.
Ito et al., “Mechanical Stress Effect of Etch-Stop Nitride and its Impact on Deep Submicron Transistor Design”, International Electron Devices Meeting, IEEE, 2000, 10.7.1-10.7.4.
Shimizu et al., “Local Mechanical-Stress Control (LMC): A New Technique for CMOS-Performance Enhancement”, International Electron Devices Meeting, IEEE, 2001, 19.4.1-19.4.4.
Ota et al., “Novel Locally Strained Channel Technique for High Performance 55nm CMOS”, International Electron Devices Meeting, IEEE, 2002, pp. 27-30, 2.2.1-2.2.4.
Zhang et al. “A N

Affiliated with

Also associated with

Rating

Gate electrode stress control for finFET performance... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Gate electrode stress control for finFET performance..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Gate electrode stress control for finFET performance... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2658181