Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-09-11
2002-03-12
Abraham, Fetsum (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S360000
Reexamination Certificate
active
06355959
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor device structures and, in particular, to electrostatic discharge protection structures for use with integrated circuits.
2. Description of the Related Art
Electrostatic Discharge (ESD) protection devices are commonly employed in an integrated circuit (IC) to protect electronic devices in the IC from spurious pulses of excessive voltage (e.g., an ESD event, Human Body Model [HBM] event, or Electrical Overstress [EOS] event). See, for example, S. M. Sze,
Electrostatic Discharge Damage
, in VLSI Technology, Second Edition, 648-650 (McGraw Hill, 1988). A variety of conventional ESD protection devices that make extensive use of diodes, metal-oxide-semiconductor field effect transistors (MOSFETs), and bipolar transistors are known in the field. For example, conventional ESD protection devices for use with CMOS integrated circuits include Grounded Gate MOS (GGMOS) ESD protection structures and Low Voltage Triggered Silicon Controlled Rectifier (LVTSCR) ESD protection structures. Descriptions of these and other conventional ESD protection structures are available in Haigang, et al., A Comparison Study of ESD Protection for RFICs: Performance vs. Parasitics, 2000 IEEE Radio Frequency Integrated Circuits Symposium, 235-237 (2000); U.S. patent application for “MOSFET Structure For Use in ESD Protection Devices” (filed Jul. 17, 2000; application number not yet assigned) and U.S. patent application No. 09/205,110 (filed Dec. 3, 1998), each of which is hereby fully incorporated by reference.
Conventional MOSFET structures are designed to exhibit breakdown characteristics only at voltages well above their standard operating supply voltage. However, during an ESD event, GGMOS ESD structures exhibit current conduction via a parasitic lateral bipolar mechanism. For a further description of current conduction in GGMOS ESD structures via a parasitic lateral bipolar mechanism, see E. A. Amerasekera et al., ESD in Silicon Integrated Circuits, sections 3.5.2 and 3.6 (John Wiley & Sons, 1995), which are hereby fully incorporated by reference.
ESD events can be of either a negative polarity or a positive polarity. Conventional GGMOS and LVTSCR ESD protection structures can only protect electronic devices in an IC from a single polarity ESD event. Thus, two such structures are required to protect electronic devices in an IC from ESD events of both polarities.
The ESD protection capability of ESD protection devices is characterized by their snapback holding voltage and their maximum snapback current. ESD protection capability is improved at lower snapback holding voltages and higher maximum snapback current. Conventional GGMOS and LVTSCR ESD protection structures operate via an avalanche-injection conductivity modulation mechanism. This mechanism, however, provides a relatively high snapback holding voltage and a relatively low snapback current. In addition, conventional ESD protection structures are subject to thermal overheating and associated irreversible damage and/or instability during an ESD event.
Still needed in the field, therefore, is an ESD protection structure that can protect electronic devices in an IC from ESD events of both positive and negative polarities, has a low snapback holding voltage and a high maximum snapback current, and is relatively immune to thermal overheating.
SUMMARY OF THE INVENTION
The present invention provides an ESD protection structure for use with ICs that can protect electronic devices in an IC from ESD events of both positive and negative polarities, has a low snapback holding voltage and a high maximum snapback current, and is relatively immune to thermal overheating.
ESD protection structures for use with ICs according to the present invention include a semiconductor substrate (e.g., a silicon substrate) of a first conductivity type (typically P-type), a first well region of a second conductivity type (typically N-type) disposed in the semiconductor substrate, and a second well region, also of the second conductivity type, disposed in the semiconductor substrate. The first and second well regions are separated by a gap region of the first conductivity type that is disposed in the semiconductor substrate.
Also included in ESD protection structure according to the present invention are a gate silicon dioxide layer overlying the gap region and a gate electrode (e.g., a polysilicon gate electrode) overlying the gate silicon dioxide layer. The ESD protection structures further include a first floating region and a second floating region, each of the second conductivity type, disposed in the first well region and second well region, respectively. The first and second floating regions are adjacent to the gap region. In addition, the ESD protection structures include first and second contact regions of the first conductivity type disposed on the first and second well regions, respectively, and spaced apart from the first and second floating regions, respectively. The ESD protection structures further include first and second contact regions of the second conductivity type that are also disposed on the first and second well regions, respectively, and also spaced apart from the first and second floating regions, respectively.
ESD protection structures according to the present invention can be thought of as a variant of an MOS-TRIAC structure that provides for ESD protection capability by the distinctive addition of first and second floating regions, a P-type contact region and an N-type contact region in each of the first and second well regions and a gate electrode.
During operation, ESD protection structures according to the present invention undergo primary breakdown via a low current avalanche breakdown mechanism in the gap region between the first and second floating regions. Following this low current avalanche breakdown, and when the current has exceeded a critical switching value, the ESD protection structures exhibit “double injection” of holes and electrons from an N-type and a P-type contact region, one in each of the first and second well regions, to attain a high maximum snapback current. This high maximum snapback current is attributed to mutual space charge neutralization and conductivity modulation in the gap region (and an associated reduction in the electric field). The primary breakdown and critical switching value of the ESD protection structure can be controlled by an applied or induced potential on the gate electrode.
An advantage of ESD protection structures according to the present invention is that they are symmetrical (i.e., each of the first and second well regions has both an N-type contact region and a P-type contact region disposed therein). The ESD protection structures can, therefore, protect electronic devices in an IC from ESD events of both a negative and a positive polarity. ESD protection structures for use with ICs according to the present invention can be manufactured using conventional semiconductor manufacturing techniques (e.g., 0.18 micron CMOS process technologies) and are, therefore, compatible for use with CMOS integrated circuits.
REFERENCES:
patent: 6265251 (2001-07-01), Jan et al.
Carneiro Manuel
Hopper Peter J.
Vashchenko Vladislav
Abraham Fetsum
National Semiconductor Corporation
Pillsbury & Winthrop LLP
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