Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2001-03-20
2003-02-11
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S083000, C326S021000, C327S108000, C327S396000, C327S393000
Reexamination Certificate
active
06518791
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2000-078882, filed Mar. 21, 2000; and No. 2000-229158, filed Jul. 28, 2000, the entire contents of both of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a gate driver for making control so as to turn ON/OFF an output element such as a power MOSFET, an IGBT (Insulated Gate Bipolar Transistor), or the like, and a power converter in which the gate driver and the output element are integrated in one-chip.
FIG. 1
is a block diagram showing the schematic structure of a conventional gate driver and a power converter. This circuit is constructed by an edge detection circuit
1
, an ON pulse generation circuit
2
, an OFF pulse generation circuit
3
, a status hold circuit
4
, an output element
9
, and the like. The part surrounded by a broken line corresponds to the gate driver
10
. The power converter is constructed by the gate driver
10
and the output element
9
.
The edge detection circuit
1
is inputted with a control input signal and a protect operation signal and detects rise and fall of the control input signal. The ON pulse generation circuit
2
generates an ON pulse Pon in response to a leading edge of the control input signal detected by the edge detection circuit
1
, and the OFF pulse generation circuit
3
generates an OFF pulse Poff in response to the trailing edge of the input signal detected by the edge pulse detection circuit
1
. The status hold circuit
4
is inputted with an ON pulse Pon outputted from the ON pulse generation circuit
2
, and a OFF pulse Poff outputted from the OFF pulse generation circuit. Based on the ON pulse Pon and OFF pulse Poff, the gate driving status of the output element
9
is held. That is, the status hold circuit
4
drives the gate of the output element
9
to turn on and maintains it turned on until the OFF pulse Poff is inputted.
When a leading edge is detected (timing t
1
) as shown in
FIG. 2
in the structure as described above, an ON pulse Pon is outputted from an ON pulse generation circuit
2
and the gate of the output element
9
is driven to turn on. This ON status is held by the status hold circuit
4
. When a trailing edge of the control input signal is detected by the edge detection circuit
1
(timing t
2
), an OFF pulse Poff is outputted from the OFF pulse generation circuit
3
, and driving of the gate of the output element is stopped and turned off. This off status is held by the status hold circuit
4
.
Meanwhile, when the protect operation signal rises in a state where a leading edge of the control input signal is detected by the edge detection circuit
1
and the gate of the output element is driven to turn on, the control input signal falls inside the edge detection circuit
1
. This fall is detected and an OFF pulse Poff is outputted from the OFF pulse generation circuit
3
(timing t
4
), and driving of the output element
9
is stopped to turn off.
However, no OFF pulse Poff is generated even when an operation error which causes the output element
9
to turn on occurs (timing t
5
) due to some reason (noise, a voltage shift of an output part, or the like) and the operation error causes a protect operation signal to rise, in a state in which the control input signal indicates OFF (“L” level) of the output element
9
. This is because the structure is arranged such that the control input signal is fixed to the “L” level inside the edge detection circuit
1
in synchronization with the protect operation signal. Therefore, at the timing t
6
, the control input signal is at “L” level and no trailing edge exists. Consequently, no OFF pulse Poff is generated. As a result, it is not possible to eliminate an abnormal operation which causes the output element
9
to turn on although the output element
9
should originally be turned off, but the output element
9
holds the on status, leading to breakdown.
FIG. 3
is a circuit diagram showing another structural example of a conventional gate driver. This gate driver
100
controls output elements (switching elements which are IGBTs in this case)
6
and
8
having a push/pull structure, and comprises a high-side gate driver circuit
101
for controlling a high-side switching element
6
to turn ON/OFF, a low-side gate driver circuit
102
for controlling the low-side switching element
8
to turn ON/OFF. The high-side gate driver circuit
101
is constructed by an edge detection circuit
1
′, an ON pulse generation circuit
2
, an OFF pulse generation circuit
3
, a latch circuit (corresponding to the status hold circuit
4
in
FIG. 1
)
4
′, a drive circuit
5
, and the like. The low-side gate driver circuit
102
is structured to include a drive circuit
7
.
The gate driver
100
drives the switching elements
6
and
8
in the high and low sides at individual operation voltages, respectively, so that the circuit in the high-side system and the circuit in the low-side system are operated at different reference voltages, respectively. The edge detection circuit
1
′, ON pulse generation circuit
2
, and OFF pulse generation circuit
3
in the high-side gate driver circuit
101
are created by circuits of the low-side system, and the latch circuit
4
′ and drive circuit
5
are created by circuits of the high-side system. Also, the drive circuit
7
is created by a circuit of the low-side system. Further, the high-side input signal HS and the low-side input signal LS are both inputted as signals based on a reference voltage of the low-side system.
The high-side input signal HS for control the high-side switching element
6
to turn ON/OFF is inputted to the edge detection circuit
1
′, and the detection output from this edge detection circuit
1
′ is supplied to the ON pulse generation circuit
2
and the OFF pulse generation circuit
3
. The ON pulse generation circuit
2
generates an ON pulse Pon in response to the leading edge of the high-side input signal HS detected by the edge detection circuit
1
′. Also, the OFF pulse generation circuit
3
generates an OFF pulse Poff in response to the trailing edge of the high-side input signal HS detected by the edge detection circuit
1
′. The ON pulse Pon outputted from the ON pulse generation circuit
2
and the OFF pulse Poff outputted from the OFF pulse generation circuit
3
are supplied to the latch circuit
4
′ so that ON/OFF information of the high-side switching element is held. Further, a high-side gate signal HG is outputted from the drive circuit
5
, based on the latch circuit
4
′, and is supplied to the gate of the high-side switching element
6
, so that this high-side switching element
6
is driven.
Meanwhile, the low-side input signal LS for controlling the low-side switching element
8
to turn ON/OFF is supplied to the drive circuit
7
. The low-side gate signal LG outputted from this drive circuit
7
is supplied to the gate of the low-side switching element
8
, so that this low-side switching element
8
is driven.
The high-side switching element
6
and the low-side switching element
6
are constructed in a push/pull structure. The collector and emitter of the high-side switching element
6
are respectively connected to a power supply VC and an output terminal
11
. The collector and emitter of the low-side switching element
8
are respectively connected to the output terminal
11
and a ground point GND.
Next, with respect to the structure as described above, operation will be explained with reference to a timing chart shown in FIG.
4
. Driving of the high-side switching element
6
is carried out as follows. When a leading edge (timing t
1
) of the high-side input signal HS is detected by the edge detection circuit
1
′, an ON pulse Pon is generated from the ON pulse generation circuit
2
. When a trailing edge of the high-side input signal HS (timing t
2
) is detected, an OFF pulse Poff is generated from the
Kojima Tsutomu
Takahashi Morio
Takei Hiroshi
Yamashita Akira
Kabushiki Kaisha Toshiba
Tan Vibol
Tokar Michael
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