Gate driver circuit and display device having the same

Details Gate driver circuit and display device having the same Gate driver circuit and display device having the same

2005-11-29

2009-06-16

Hjerpe, Richard (Department: 2629)

Computer graphics processing and selective visual display system

Plural physical display element control system

Display elements arranged in matrix

Reexamination Certificate

active

07548228

ABSTRACT:
The first shift register applies (4n−3)-th and (4n−2)-th gate signals to (4n−3)-th and (4n−2)-th gate lines, respectively, in response to a first clock signal, a second clock signal having a delayed phase by 1H time with respect to the first clock signal, and a third clock signal having opposite phase to the first clock signal. The second shift register applies (4n−1)-th and 4n-th gate signals to (4n−1)-th and 4n-th gate lines, respectively, in response to the first clock signal, the third clock signal, and a fourth clock signal having opposite phase to the second clock signal. Therefore, a number of transistors in the first and second shift registers may be reduced.

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