Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2006-01-27
2009-12-15
Lefkowitz, Sumati (Department: 2629)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
Reexamination Certificate
active
07633481
ABSTRACT:
A gate drive portion for a display device including multiple pixels having first and second sub-pixels includes a first shift register generating a first output signal in response to a first gate clock signal, a second shift register generating a second output signal in response to a second gate clock signal, a level shifter coupled to the first and second shift registers and amplifying the first and second output signals, and an output buffer coupled to the level shifter and generating first and second gate signals. The first gate signal is generated in synchronization with the first gate clock signal and the second gate signal is generated in synchronization with the second gate clock signal. Accordingly, the charging time of the first and second sub-pixels may be improved by separately driving the odd-numbered and even-numbered sub-pixels and the visibility of the LCD device may also be improved.
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Kim Woo-Chul
Lee Jun-Pyo
Moon Seung-Hwan
Son Sun-Kyu
Amadiz Rodney
Cantor & Colburn LLP
Lefkowitz Sumati
Samsung Electronics Co,. Ltd.
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