Gate dielectrics of different thickness in PMOS and NMOS...

Details Gate dielectrics of different thickness in PMOS and NMOS... Gate dielectrics of different thickness in PMOS and NMOS...

2011-08-09

2011-08-09

Richards, N Drew (Department: 2895)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S585000

Reexamination Certificate

active

07994037

ABSTRACT:
By providing a gate dielectric material of increased thickness for P-channel transistors compared to N-channel transistors, degradation mechanisms, such as negative bias threshold voltage instability, hot carrier injection and the like, may be reduced. Due to the enhanced reliability of the P-channel transistors, overall production yield for a specified quality category may be increased, due to the possibility of selecting narrower guard bands for the semiconductor device under consideration.

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Translation of Official Communication from German Patent Office for German Patent Application No. 10 2008 035 805.3-33 dated May 5, 2009.

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