Gate dielectric with self forming diffusion barrier

Details Gate dielectric with self forming diffusion barrier Gate dielectric with self forming diffusion barrier

2000-02-29

2001-09-11

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

C438S585000, C438S624000

Reexamination Certificate

active

06287897

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a gate dielectric for a CMOS device that is thermally stable and resistant to dopant diffusion, and a method of fabricating a CMOS device employing such a gate dielectric.
In complementary metal oxide silicon (CMOS) technology, a need to enhance the speed and increase the density of CMOS integrated circuits (IC's) has resulted in the evolution of transistor scaling, accompanied by progressively thinner gate dielectric oxide. Reduction in the thickness of a gate dielectric provides increased drive current, with resultant increased speed. In addition, a thinner gate dielectric offers enhanced control of channel charge, thereby reducing short channel effects. However, the fabrication of thinner gate oxides presents gate leakage current and reliability issues. In particular, physically thinner gate oxides exhibit gate leakage increasing exponentially with reduction in thickness.
The most common gate dielectric material in CMOS devices has been silicon oxide (SiO
2
) or SiO
2
/silicon nitride (Si
3
N
4
) or oxynitride (SiO
x
N
y
) combinations. In the case of combinations, the Si
3
N
4
or SiO
x
N
y
often is employed as a diffusion barrier layer. As the thickness of the SiO
2
and Si
3
N
4
films is reduced and approaches the 20 Å regime, substantial problems begin to appear. These problems include the production of incomplete films leading to leaky gates and low breakdown, charge trapping at the gate channel interface as well as in the bulk silicon, and difficulty of manufacture and thickness control.
One solution to the problems of thinner gate dielectrics is to use thick dielectric films having high dielectric constants (high K). In this manner, the actual physical thickness of the gate dielectric film can be large, while the electrical equivalent thickness relative to the SiO
2
or SiO
2
/Si
3
N
4
films can be scaled. The equivalent thickness (“teq”) of a high dielectric constant material to SiO
2
, for example, may be calculated by the formula:
teq=tphy (SiO
2
/high K)
where “tphy” is the actual thickness of the substitute high dielectric constant material film, SiO
2
is the dielectric constant of SiO
2
(K=3.8), and high K is the dielectric constant of the substitute high dielectric constant film.
Any practicable gate dielectric film structure must meet at least two vital criteria. Firstly, the dielectric must be thermally stable with respect to the silicon substrate, and, secondly, it must be able to serve as a dopant barrier. Dopant barrier capability, particularly to boron, is essential if the gate dielectric is to be useful in a CMOS structure, since boron is used to dope polysilicon gates in p-channel field effect transistors (“PFETs”) . A dielectric film structure having a high dielectric constant (or a small teq relative to SiO
2
) and an effective method of fabrication thereof is needed for development of improved performance CMOS devices.
SUMMARY OF THE INVENTION
Now, according to the present invention, a high K gate dielectric material is provided which, during fabrication, forms a dopant barrier layer. The present invention utilizes a high K dielectric material as the primary gate dielectric. Suitable high K dielectric materials are metallic oxide or metallic silicate materials. Such materials may be selected from the group consisting of Ta
2
O
5
, Al
2
O
3
, TiO
2
, ZrO
2
, Y
2
O
3
, La
2
O
3
, and HfO
2
, or silicates of Ta, Al, Ti, Zr, Y, La, and Hf, and the like. Preferably, the high K material comprises Zr or Al oxides or silicates. The dielectric material preferably is deposited on a silicon substrate and then forms a silicon nitride dopant diffusion barrier layer by implantation of nitrogen during fabrication of an electronic device. Preferably, an upper dopant diffusion barrier layer and a lower dopant diffusion barrier are formed on the top and bottom surfaces of the metallic oxide dielectric layer. Preferably, the top and bottom diffusion barriers comprise about 5 Å to about 10 Å layers of oxy nitride film. The resultant gate dielectric layer preferably has an equivalent oxide thickness (EOT) of less than about 20 Å SiO
2
. Utilizing Ta
2
O
5
as the high dielectric material requires about a 40 Å layer to accomplish the desired 20 Å SiO
2
EOT. Other preferred thermodynamically stable, high dielectric materials such as TiO
2
(K=40) and Al
2
O
3
(K=12) would require about 60 Å and 100 Å thick dielectric layers respectively.


REFERENCES:
patent: 4411929 (1983-10-01), Sato et al.
patent: 4510172 (1985-04-01), Ray
patent: 4683637 (1987-08-01), Varker et al.
patent: 4891684 (1990-01-01), Nishioka et al.
patent: 5229310 (1993-07-01), Sivan
patent: 5783469 (1998-07-01), Gardner et al.
patent: 5783798 (1998-07-01), Abraham
patent: 5891798 (1999-04-01), Doyle et al.
patent: 5981798 (1999-04-01), Doyle et al.
patent: 6180469 (2001-01-01), Pramanick et al.

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