Gate dielectric

Details Gate dielectric Gate dielectric

2001-10-29

2004-03-02

Hu, Shouxiang (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S410000, C257S310000

Reexamination Certificate

active

06700171

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the technology of semiconductors. More specifically, the present invention relates to gate dielectrics for metal-insulator-semiconductor capacitors and transistors, and methods for forming such.
BACKGROUND OF THE INVENTION
Field effect transistors (FETs) are common in the electronics industry.
FIG. 1
discloses a typical FET
10
in cross-section. In a FET, a portion of the substrate
12
near the surface is designated as the channel
14
during processing. Channel
14
is electrically connected to source
16
and drain
18
, such that when a voltage difference exists between source
16
and drain
18
, current will tend to flow through channel
14
. The semiconducting characteristics of channel
14
are altered such that its resistivity may be controlled by the voltage applied to conductive gate
20
, a conductive layer overlying channel
14
. Thus by changing the voltage on conductive gate
20
, more or less current can be made to flow through channel
14
. Conductive gate
20
and channel
14
are separated by gate dielectric
22
. The gate dielectric is insulating, such that between gate
20
and channel
14
little or no current flows during operation (although “tunneling” current is observed with thin dielectrics as is described below). However, the gate dielectric allows the gate voltage to induce an electric field in channel
14
, giving rise to the name “field effect transistor.” Typically, the gate dielectric material is silicon dioxide (SiO
2
.)
Generally, integrated circuit performance and density may be enhanced by “scaling”, that is by decreasing the size of the individual semiconductor transistors on a chip. Unfortunately, field effect semiconductor transistors produce an output signal that is proportional to the length of the channel, such that scaling reduces their output. This effect has generally been compensated for by decreasing the thickness of gate dielectric
22
, thus bringing the gate in closer proximity to the channel and enhancing the field effect.
By 2005, it is anticipated that SiO
2
gate oxides of 1.0 to 1.5 nm thickness will be required for the so-called 100 nm technology node. At these thicknesses, the direct tunneling current through SiO
2
layers begins to become prohibitive.
Although further scaling of FETs is still possible, scaling of the gate dielectric thickness has almost reached its practical limit with the conventional gate dielectric material, silicon dioxide. Further scaling of silicon dioxide gate dielectric thickness will involve a host of problems: extremely thin layers allow for large leakage currents due to direct tunneling through the oxide. Because such layers are formed literally from a few layers of atoms, exacting process control is required to repeatably produce such layers. Uniformity of coverage is also critical because device parameters may change dramatically based on the presence or absence of even a single monolayer of dielectric material. Finally, such thin layers form poor diffusion barriers to impurities.
Realizing the limitations of silicon dioxide, researchers have searched for alternative dielectric materials which can be formed in a thicker layer than silicon dioxide and yet still produce the same field effect performance. One alternative for achieving low equivalent oxide thicknesses is metal oxides, such as tantalum pentoxide, titanium dioxide, and barium strontium titanate. However, researchers have found formation of such metal oxides as gate dielectrics to be problematic since they can be directly reduced by the silicon substrate resulting in the formation of a layer of SiO
2
between the films and the Si substrate. Metal oxides such as ZrO
2
, HfO
2
, many of the rare-earth oxides, and the analogous metal silicates of the forgoing metal oxides, do not undergo such reactions directly; however, at typical deposition temperatures, the oxygen ambient or oxygen-containing precursor required to form them tends to also oxidize the silicon substrate, producing an oxide layer at the interface between the substrate and the gate dielectric. These interfacial layers can also be formed if the dielectric layers are annealed in an environment containing oxygen or oxygen-bearing molecules. The presence of this interfacial oxide layer increases the effective oxide thickness, reducing the effectiveness of the alternative gate dielectric approach.
The use of alternative dielectric materials, such as silicon nitride, has also been considered as a means to increase the gate dielectric constant and also to serve as a diffusion barrier to dopants in the gate material. However, the current silicon nitride fabrication techniques on Si (100) result in an amorphous nitride or oxynitride layer which may exhibit deleterious interface states (traps) which degrade ultimate device performance.
A separate problem with silicon dioxide dielectrics is that the extremely small thicknesses allow unacceptable leakage currents as a result of electrons tunneling from the gate to the drain regions of transistors. Since silicon nitride has a larger bulk dielectric constant than silicon dioxide (about 7 compared to about 3.9), a thicker silicon nitride layer can be used which has the same capacitance density as a thinner silicon dioxide layer. Since electron tunneling currents depend exponentially on layer thickness, even an increase in dielectric thickness of about 10 to about 20 Angstroms could reduce leakage current by many orders of magnitude.
Candidate materials for gate dielectrics have been arranged by the International Technology Roadmap for Semiconductors (ITRS) into four categories:
1. Medium &kgr; (10-20) (amorphous) Unary oxides: including Ta
2
O
5
, TiO
2
, ZrO
2
, HfO
2
, Y
2
O
3
, La
2
O
3
, Gd
2
O
3
, Sc
2
O
3
, etc.
2. Medium &kgr; (10-20) (amorphous) Silicates: including (Zr, Hf, La, Ti . . . )—SiO
4
, etc.
3. High &kgr; (>20) (amorphous) oxides: including LaAlO
3
, ZrTiO4, (Zr, Sn)TiO
4
SrZrO
4
, etc.
4. High &kgr; (>20) (single crystal) oxides: LaAl
3
O
4
, BaZrO
3
, Y
2
O
3
, La
2
O
3
, etc.
Films of these types have been deposited on silicon using a number of techniques including electron-beam evaporation, chemical vapor deposition and its variants, molecular beam epitaxy and sputtering (for example, see U.S. Pat. No. 6,093,944 issued Jul. 25, 2000, which is incorporated herein by reference). However, many of these candidate materials have been observed to react with the semiconductor substrate to form unintentional intermediate layers having lower dielectric constant than the pure oxide, i.e. the desired high-&kgr; oxide/substrate structure actually becomes high-&kgr; oxide/mixed (high-&kgr;, SiO
x
)/substrate. Also, many of these materials form polycrystalline films on silicon. This leads to high leakage current and unwanted defects, and also makes the films susceptible to further crystallization and instability during thermal device processing.
It has been demonstrated that both Zr and Hf silicate (ZrSi
x
O
y
, HfSi
x
O
y
) gate dielectric layers, of category 2, can be produced having amorphous structure, low leakage current, reasonably high dielectric constant and good thermal stability in contact with silicon. These transition-metal-silicates have stoichiometries most-closely resembling pseudobinary alloys; i.e., mixtures of SiO
2
and the metal oxide. A disadvantage of this approach is that the silicate has a lower dielectric constant than the pure metal-oxide. The films have metal contents of about 2-8 atomic %. Although the metal content in these films may potentially be increased, it has been noted that increasing the metal content significantly decreases the temperature at which the films crystallize or phase separate resulting in unfavorable conformations.
Use of other materials has been disclosed in U.S. Pat. No. 6,291,867 B1 issued Sep. 18, 2001 and U.S. Pat. No. 6,277,681 B1 issued Aug. 21, 2001, both of which are incorporated herein by reference.
Therefore, what is needed is a high dielectric constant material to be used as the gate dielectric i

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