Gate-clocked domino circuits with reduced leakage current

Details Gate-clocked domino circuits with reduced leakage current Gate-clocked domino circuits with reduced leakage current

2005-10-04

2005-10-04

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S112000

Reexamination Certificate

active

06952118

ABSTRACT:
A gate-clocked domino circuit with reduced leakage current during an inactive state, where domino stages in the domino circuit have long channel length transistors in the pre-charge paths. During an inactive state, the domino stages are put in an evaluation state and are discharged.

REFERENCES:
patent: 5598114 (1997-01-01), Jamshidi
patent: 5625303 (1997-04-01), Jamshidi
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patent: 5982197 (1999-11-01), Ono et al.
patent: 6229340 (2001-05-01), Hagihara
patent: 6429689 (2002-08-01), Allen et al.
patent: 6707318 (2004-03-01), Kumar et al.
patent: 6732136 (2004-05-01), Chen et al.
patent: 2004/0194037 (2004-09-01), Jamshidi et al.
patent: 2004/0252574 (2004-12-01), Jamshidi
Pending U.S. Appl. No. 09/044,392, P5042, entitled: “Domino-Logic Gates With Improved Noise Immunity”, filed on Mar. 18, 1998.

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