Gate array semiconductor integrated circuit device

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257204, 257205, 257347, 257351, 257368, H01L 2710, H01L 2701, H01L 2976

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active

056335245

ABSTRACT:
In order to improve a withstand voltage and implement a gate array SOI semiconductor integrated circuit device having a large gate width, a region consisting of end cells (49) is provided on each end of a region formed by repeatedly arranging basic cells (BC) consisting of both transistor regions (32, 33) in a first direction and while symmetrically arranging the same to be folded in a second direction. Both ends of a channel region of a PMOS transistor (42) are drawn out in the second direction to provide a P-type semiconductor layer just under a field shielding gate electrode (FG), and this semiconductor layer is drawn also in the first direction to be connected with a P-type semiconductor layer of the end cell (49). A first source potential is applied to a region (PBD) which is bonded with one of the P-type semiconductor layers. Also as to an NMOS transistor (41) which is adjacent through a field oxide film (FO), on the other hand, an N-type semiconductor layer is similarly provided so that this N-type semiconductor layer is also connected with that of the end cell (49). A second source potential is applied to a region (NBD).

REFERENCES:
patent: 5327000 (1994-07-01), Miyata et al.
patent: 5440161 (1995-08-01), Iwamatsu et al.
patent: 5495124 (1996-02-01), Terashima
1993 IEEE, IEDM, pp. 475-478, 1993, T. Iwamatsu, et al., "CAD-Compatible High-Speed CMOX/SIMOX Technology Using Field/Shield Isolation For 1M Gate Array".

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