Gate array integrated circuit device and method thereof for prov

Details Gate array integrated circuit device and method thereof for prov Gate array integrated circuit device and method thereof for prov

1985-12-04

1988-12-13

Hecker, Stuart N.

Static information storage and retrieval

Format or disposition of elements

365 63, 365189, G11C 510

Patent

active

047916079

ABSTRACT:
A gate array integrated circuit incorporating memories and a method therefore can realize various bit/word constructions according to customer's requests. The gate array integrated circuit of the present invention provides a basic cell array region in which a plurality of basic cells are arranged, a memory cell matrix region in which a plurality of memory cells are arranged, and a plurality of peripheral circuits which include address input circuits and decoders to access the memory cells.

REFERENCES:
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patent: 4527254 (1985-07-01), Ryan et al.
patent: 4535423 (1985-08-01), Nozaki et al.
patent: 4590588 (1986-05-01), Itoh et al.
patent: 4660174 (1987-04-01), Takemae et al.
patent: 4688197 (1987-08-01), Novak et al.
IBM Technical Disclosure Bulletin, "Implementing Array and Logic Functions on a Single Chip", Pomeranz et al., vol. 20, No. 10, Mar. 1978, pp. 3921-3922.
Patent Abstracts of Japan, vol. 8, No. 59, Mar. 17, 1984.
Patent Abstracts of Japan, vol. 6, No. 222, Nov. 6, 1982.

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