Gate array for accelerating access to a random access memory

Details Gate array for accelerating access to a random access memory Gate array for accelerating access to a random access memory

1995-05-23

1997-06-03

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Including specified plural element logic arrangement

326 39, 326 40, G11C 1134

Patent

active

056361645

ABSTRACT:
An apparatus for rapidly determining a control parameter t=t.sub.0 at which the sum S of n functions F.sub.i (i=1, . . . n) reaches a minimum, a maximum, or a given value, wherein each function F.sub.i (t) changes its first derivative only at given discrete values t.sub.ij of the control parameter t is described. The apparatus has a random access memory (RAM) addressed by the values t.sub.ij, a circuit for summing the second derivatives of the functions, a circuit to perform a double integration to evaluate S, and a comparator to determine the optimum control value; also disclosed is a new gate array (GA) which rapidly reproduces the addresses used to address the RAM while skipping all others. This gate array is advantageously used as a part of the apparatus for determining a control parameter. Further, the use of the devices in a communication network is described.

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