Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-09-06
2003-06-03
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06574786
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to the field of tools and methods for integrated circuit design. In particular the invention relates to tools and methods for generating a library of cells for use on mask-programmed gate array integrated circuit designs.
STATEMENT OF THE PROBLEM
Integrated circuits require a sequence of masking steps during fabrication, these masking steps are interspersed with a variety of oxide growth, etching, ion implanting, deposition, and other processing steps. Each masking step typically requires use of a costly mask and defines a single layer of the many layers of the resulting integrated circuit.
Mask-programmed gate array integrated circuits are manufactured with a sequence of masks. They use a regular pattern of low-level structures so that low-level masks may be common to several integrated circuit types, but use higher-level masks custom tailored to each type of circuit manufactured. With this technique, fewer custom masks need be manufactured for each type of circuit than with full-custom designs. It is also possible to stockpile partially-manufactured integrated circuits so that first prototypes of new integrated circuit types can be produced more quickly than with fully customized mask sets. The partially manufactured circuit as defined by the low-level masks can be described as a base array.
A typical CMOS gate array has a large number of low-level cells, each low-level or transistor cell containing a fixed pattern of transistors of P and N channel types. These cells are produced by the common low-level masks, some of the transistors of these cells are interconnected by customized higher-level interconnect produced by the higher-level customized masks to form the desired circuit.
In designing a digital integrated circuit, most engineers do not design at the transistor level. Most engineers design circuits comprising a hierarchy of logical cells interconnected to perform a desired function. Typical logical cells include RS, D or JK flip-flops, latches, inverters, and adders, as well as NAND, NOR, XOR, OR, and AND gates. These logical cells are often selected from a cell library for placement into the design.
Cells of a logical cell library are often characterized for speed so that they may be modeled at the gate level. Simulations of the circuits may then be performed at gate level for verification of the integrated circuit design.
It is known that a logical cell library may be constructed such that each cell of the library is built from gate array transistor cells with logical-cell internal interconnect. The logical-cell internal interconnect connects transistors of the transistor cells into a circuit for performing the function of the logical cell. These cells may then be placed and connected to form the logic of the integrated circuit. For example, a logical cell library built on gate-array transistor cells of peculiar form is described in U.S. Pat. No. 6,031,982. The libraries of logical cells provided by different manufacturers, or even by a single manufacturer for different processes, often contain different logical cell types.
Once the cell library is built, a netlist is generated for the integrated circuit. This netlist is generated through synthesis or extraction of a schematic as known in the art. The netlist indicates the logical cells required for the integrated circuit and their interconnections.
Logical cells are placed in the layout of the integrated circuit such that they align with the transistor cells of the gate array. Placement may be by hand or may be accomplished by automatic placement software as known in the art. Next, the interconnect specified by the netlist is generated and inserted into the layout; this interconnect may be generated by hand or by routing software as known in the art. Once the interconnect is generated, the logical cell's parasitic resistance and capacitance parameters may be extracted for final verification. Masks are then made for the upper levels of the integrated circuit and used to transform base arrays into completed integrated circuits.
Masks used for manufacture of integrated circuits are subject to design rules that vary with the process on which the circuits are to be made. Processes vary from manufacturer to manufacturer as well as with the level of technology. These rules specify minimum dimensions for shapes as well as minimum spaces between shapes. They also specify relationships between shapes defined by different masks. For example, a design rule may require that a contact be overlapped by metal of a specified width.
The base array of a gate-array design also imposes constraints on the higher-level interconnect. For example, connections to the transistors can only be made at particular locations in each transistor-level cell; these locations may change if the cell is modified to fit design rules for a different process. Similarly, these locations may change if the cell is modified for other reasons such as to improve its radiation hardness or latchup resistance.
Construction of a base array is typically done by manual layout. Construction of a library of logical cells for a specific process is typically done by manual layout of logical-cell internal interconnect. These time-consuming tasks must be repeated for each base array design and process on which the library is to be supported. New processes and base array designs are being introduced, and design rules for others refined, at an increasingly rapid pace, making such manual construction expensive.
It is desirable to have a way to quickly and automatically generate a logical cell library and base array for each process to be used. This cell library should have a standardized selection of logical gates, flip-flops, and other cells so that circuit designs initially created for one process and base array combination can be quickly converted for manufacture on another process and base array. This is particularly important to foundry-independent semiconductor companies such as Aeroflex UTMC because of the need to quickly map designs for manufacture at different wafer fabrication plants.
Available Tools
Cadence Design Systems, Inc. (Cadence) is a supplier of computer-aided design software to the integrated circuit design industry. Many Cadence layout tools support the SKILL language for automating manual tasks and customizing the software.
A technology file is a way of representing information including the design rules of a particular process in machine-readable form such that these rules may be used by design software tools. Cadence tools support a machine-readable technology file having a physical rules class. The physical rules class permits definition of spacing rules for the following:
width of objects on a particular layer (minWidth)
the minimum space of a notch in an object on a particular layer (minNotch)
the minimum distance allowed between objects (minSpacing)
the amount of space required when one object encloses another (minEnclosure)
Relative Object Design (ROD) is a SKILL language procedural interface provided by Cadence which allows a programmer to:
Assign names to geometrical objects, including rectangle instances and paths;
Access objects and points through all levels of hierarchy,
Align ROD objects to each other or to specific coordinates;
Create user-defined handles for aligning of objects including interconnect; and
Use of a technology file to enforce spacing, width, enclosure, and overlap rules.
ROD function parameters may be set by the technology file, or can be written directly by the designer in SKILL code. These function parameters can also be set to an arithmetic combination of technology file and other parameters.
Cadence promotes use of ROD-based transistor-level parameterized cells (PCELLS) with their integrated circuit layout editors. These PCELLS are known to support generation of layout for CMOS single and multiple-gate transistors, snaked resistors, capacitors, guard rings, shielded wires, and similar component structures for use within cell layouts such as used in full-custom integrated
Patton Stacia
Pohlenz Peter Mikel
Aeroflex UTMC Microelectronics Systems, Inc.
Hogan & Hartson LLP
Kubida William J.
Lin Sun James
Meza Peter J.
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