Gate array cell

Details Gate array cell Gate array cell

1986-07-14

1987-07-21

Edlow, Martin H.

357 45, 29591, H01L 2702

Patent

active

046822011

ABSTRACT:
A gate array layout in which alternative rows include areas of devices of the same diffusion type, and all the rows run in parallel on the device. However, the diffusion areas in adjacent rows are offset with respect to one another so that only cells in alternative rows which are all of one conductivity define straight parallel columns. By providing this relative offset between adjacent rows, the contacts to the source, drain and gate of interconnected devices all lie on straight lines, thereby simplifying the metal interconnect patterns. In addition to cells along each row being immediately abutting, cells in adjacent rows are abutting (although offset with respect to each other) so that no routing channels need be reserved. By offset, it is meant that the cells of both N and P type conductivity devices each contain the same number of transistor, or source and drain diffusions lying along a given row; but at least one of the source and drain diffusions in each cell does not lie in a column with the adjacent diffusion.

REFERENCES:
patent: 4319342 (1982-03-01), Scheuerlein
"Channel-Less Gate Array Reduces Die Size" Electronic Engineering, Jun. 1983, p. 113.

Affiliated with

Also associated with

Rating

Gate array cell does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Gate array cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Gate array cell will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-210890