Gate alignment procedure in fabricating semiconductor devices

Details Gate alignment procedure in fabricating semiconductor devices Gate alignment procedure in fabricating semiconductor devices

1987-05-04

1989-04-11

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156653, 156656, 156657, 1566591, 357 41, 357 65, 430317, 430318, 437 41, 437 58, 437203, 437228, H01L 2978, H01L 21306, B44C 122, C23F 102

Patent

active

048210943

ABSTRACT:
A self-aligned metal gate is formed on a semiconductor substrate surface between a source region and a drain region of the substrate. Precise alignment of the boundaries of the gate with the boundaries of the source and drain regions is obtained by shadowing a photoresist coating over metal deposited onto the substrate surface, while photochemically dissociating the photoresist over metal deposited onto an oxide layer formed over the source and drain regions of the substrate. The developed photoresist is removed, and the undeveloped photoresist is hard-baked to serve as a protective coating for the metal between the source and drain regions. The metal over the source and drain regions is etched away, leaving the metal between the source and drain regions to function as an electronic gate.

REFERENCES:
patent: 3503124 (1970-03-01), Wanlass et al.
patent: 3997367 (1976-12-01), Yau
patent: 4532004 (1985-07-01), Akiyama

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