Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2000-02-23
2002-03-12
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S758000, C438S766000, C438S774000, C438S787000, C438S788000
Reexamination Certificate
active
06355581
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to the fabrication of silicon oxide and silicon glass films by using a High Density Plasma Chemical Vapor Deposition (HDP-CVD) technique with gas mixtures containing silane or its derivatives, necessary doping precursors, oxygen, and special gas additives.
2. Description of the Prior Art
In the fabrication of devices such as semiconductor devices, a variety of material layers are sequentially formed and processed on the substrate. For the purpose of this disclosure, the substrate includes a bulk material such as semiconductor, e.g., silicon, body, and if present, various regions of materials such as dielectric materials, conducting materials, metallic materials, and/or semiconductor materials. One of the material regions utilized in this fabrication procedure includes a silicon oxide, i.e., a material represented by the formula SiO
n
, where n=~2, or doped silicon oxide films, containing an additional doping element such as boron, phosphorus, fluorine, carbon, and their mixtures with total dopant content depending on the purpose of film application in the device. Below the common term “silicon oxide film” is used to characterize both silicon dioxide film and silicon oxide based glass films. Silicon oxide regions are utilized as insulating/passivating layers, as an electrical insulation between conducting layers, e.g., polysilicon or metal layers. Films of undoped silicon oxide are used also as a liner or as a cap layer either under or on the doped silicon oxide layers, respectively, to limit unacceptable dopant migration during subsequent processing.
Among other techniques used in semiconductor processing, silicon oxide films are deposited using Plasma Enhanced Chemical Vapor Deposition (PECVD), and High Density Plasma Chemical Vapor Deposition (HDP-CVD) techniques. The last technique assumes simultaneous deposition and sputtering of depositing films in order to improve gap-fill capability, as shown schematically in FIG.
1
.
FIG. 1
shows steps
102
formed on a semiconductor substrate
101
. The silicon oxide film
103
is deposited over the steps
102
. SiO
2
species are shown
104
on the surface of the film. Ionized Ar molecules
105
bombard the surface of the film resulting in sputtered and redeposited SiO
2
106
and vaporized SiO
2
species
107
.
The method of chemical vapor deposition of silicon oxide and doped silicon glass films at High Density Plasma conditions (HDP-CVD) with silane-oxygen based gas mixtures is used in semiconductor manufacturing mostly for sub-quarter micron Ultra Large Scale Integrated (ULSI) circuit device applications. This method is used for deposition of silicon oxide, or frequently known as undoped silicon glass (USG), phosphosilicate glass (PSG), and fluorosilicate glass (FSG). In the case of doped films, the dopant precursor, such as phosphine PH
3
, for example is added to the silane-oxygen mixture. Also, organic/inorganic silane derivatives, such as tetrafluorosilane SiF
4
or difluorosilane SiH
2
F
2
, are used either alone or in a mixture with silane.
The problem of film integrity and void formation (below the common term “voids” is used for both types of film structure imperfection) in different types of as-deposited HDP-CVD films have been found and analyzed recently, see for instance: [Ref.1]: R. Conti, L. Economikos, G. D. Parasouliotis, et al. “Processing Methods to Fill High Aspect Ratio Gaps Without Premature Construction,”
Proceedings of Fifth Dielectrics for ULSI Multilevel Int.Conf.
(DUMIC), (1999), p. 201 and [Ref.2]: J. Yota, A. Joshi, C. Nguyen et al. “Extendibility of ICP High-Density Plasma CVD for Use as Intermetal dielectric and Passivation Layers for 0.18 um Technology.”
Proceedings of Fifth Dielectrics for ULSI Multilevel Int.Conf.
(DUMIC), (1999), p.71.
The reason for void formation under HDP-CVD conditions is normally explained as a result of redeposition of the film on the nearest surfaces caused by etch/sputtering of the film with argon bombardment from the top edges of structure steps, as shown in FIG.
1
. This effect is shown in progress in FIG.
2
. Continuous deposition with etch/sputtering causes the formation of film on the steps
102
(shown in FIG.
2
A), followed by void nucleation and formation
108
at smallest spacings, as shown in FIG.
2
B and
FIG. 2C
, followed by void formation at the certain critical spacing (G
critical
,) and critical aspect ratios (AR
critical
)
109
. At the same time, a void-free film forms at a certain gap spacing, which is larger than critical, and aspect ratio, which is less than critical, as shown in
FIG. 2B
,
110
, that eventually leads to the void-free gap-fill when full film thickness is achieved, as shown in FIG.
2
C.
Detailed analysis of HDP-CVD gap-fill capability for an example of structures with vertical side wall steps, mostly desired for ULSI applications, has been performed in [Ref.3]: V. Vassiliev, C. Lin, D. Fung et al. “Properties and Gap fill Capability of HDP-PSG Films for 0.18 um Device Applications and Beyond,”
Proceedings of Fifth Dielectrics for ULSI Multilevel Int.Conf.
(DUMIC), (1999), p.235, for the above mentioned film types and two main ranges of the HDP-CVD deposition temperature, namely, less than about 400° C. and higher than about 500° C. These summarized data are presented in FIG.
3
. HDP-CVD gap-fill capability is shown for rectangular step shape with vertical side walls at low temperature (<400° C.) (line
31
), rectangular step shape with vertical side walls at high temperature (>500° C.) (line
33
), and tapered gap space with round step corners (line
35
).
Thus, HDP-CVD gap-fill capability limitations for the commonly used deposition conditions can be quantitatively described by simple equations:
AR
critical
≦k×G
critical,
where the values of coefficient k have been found to be about 13.3 &mgr;m
−1
and 20.1 &mgr;m
−1
for high and low temperature processes, respectively. To reduce void formation effects in HDP-CVD, e.g. to enhance gap-fill capability of HDP-CVD technique, the following approaches have been considered recently:
a) a decrease of the anisotropic etch (sputtering) component to deposition ratio (below “E/D ratio”) and decrease of process pressure. This helps to reduce an impact of film sputtering and, therefore, re-deposition. However, these measures cause an undesirable decrease of HDP-CVD process productivity as well as a necessity to enhance pump productivity.
b) structure rounding, as described in [Ref.3], and as shown schematically in FIG.
4
B. In fact, such rounding allows a much better HDP-CVD gap-fill capability using the same process conditions, including pressure, power, etch to deposition ratio, as shown in FIG.
3
. However, this approach is not applicable for all ULSI device structure elements.
Voids in device structures are not acceptable because of a worsening of device reliability. Therefore, it is very desirable to produce a good HDP-CVD film integrity and gap-fill capability. The prior art processes do not provide a silicon oxide layer that can satisfactorily fill gaps between the increasingly tight step features of new ULSI semiconductor devices without forming voids in between the conductor lines.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following. U.S. Pat. No. 5,915,190 to Pirkle shows a PECVD thin protection layer and a high RF-power sputter/CVD technique. U.S. Pat. No. 5,814,564 to Yao et al teaches a HDP-CVD process following by spin-on-glass (SOG) deposition and a 6-step etch process to planarize the two layers. U.S. Pat. No. 5,964,592 to Lin teaches forming 3 HDP-CVD layers th
Pradeep Yelehanka Ramachandramurthy
Sudijono John Leonard
Vassiliev Vladislav
Yu Jie
Chartered Semiconductor Manufacturing Ltd.
Kilday Lisa
Pik Rosemary L. S.
Saile George O.
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