Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-12-19
2004-09-07
Kang, Donghee (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S386000, C257S394000, C257S396000, C257S397000, C257S401000, C257S412000, C438S284000, C438S286000
Reexamination Certificate
active
06787862
ABSTRACT:
CROSS-REFERENCE
The present application is related to a copending application filed on the same date as this application entitled “Method for Fabricating a Gas Insulated Field Effect Transistor” by inventor Mark E. Murray. This application is incorporated herein by reference.
BACKGROUND
The present invention relates to a gas insulated gate field effect transistor and a method for fabricating such a transistor.
Field effect transistors have a gate, a source and a drain. A voltage applied across the gate and the substrate of the transistor causes an electric field to permeate a channel region between the source and the drain. The electric field controls current flowing through and voltage across the source and the drain. In a conventional metal oxide semiconductor field effect transistor (MOSFET) the gate is electrically isolated from the channel by an insulating layer of oxide. This creates the advantage of allowing the source and drain voltage to be controlled by a voltage applied across the gate and transistor substrate without any current flowing through the gate. Thus, significant power savings are attainable compared to bipolar junction transistors. MOSFETs may be fabricated on a very small-scale, permitting a large number of MOSFETs to reside on a small chip.
Unfortunately, MOSFETs have some significant disadvantages. Because the dielectric constant of the insulating oxide is substantially higher than air, a significant capacitance develops between the gate and the source/drain region. This limits the voltage frequencies at which MOSFETs may be successfully used. The insulating layer of oxide is subject to destruction when static electricity is applied to the MOSFET. Stability and durability of the substrate/oxide interface is less than optimal because the oxide layer is in direct contact with a crystalline silicon surface which is relatively rough. As the size of MOSFETs on an integrated circuit becomes smaller and as they become more tightly compacted the voltages and currents in one MOSFET tend to undesirably effect the operation of nearby MOSFETs.
Information relative to attempts to address these problems can be found in U.S. Pat. Nos. 5,869,379, 6,150,276, 6,188,108 B1, 6,316,294, 6,316,295 B1, 6,436,739 B1, 6,437,360 B1, 6,443,720 B1, and 6,489,683 B1.
There is a need for a gas insulated gate field effect transistor and a method for fabricating such a transistor. In such a transistor the gate is separated from the channel by a gas or a vacuum, rather than an insulating oxide.
SUMMARY
The present invention is directed to a gas insulated gate field effect transistor and a method for fabricating such a field effect transistor which addresses these problems.
The object of the present invention is to provide a gas insulated gate within a field effect transistor. This will lessen the capacitance between the gate and the source/drain region as compared to an oxide insulated MOSFET. It will also decrease the susceptibility of the insulating layer of the field effect transistor to static electricity destruction. Gasses and vacuums return to their original state typically, after the application of static electricity, while thin oxide layers are likely to be destroyed, or have their effective dielectric constants modified. An additional object of the present invention is to allow field effect transistors to be more tightly packed upon an integrated circuit chip and to be more closely positioned to neighboring field effect transistors before becoming susceptible to electrical interference from nearby field effect transistors. The fabrication step of depositing an oxide layer between the gate and the source/drain regions is avoided when gas or vacuum is used to insulate the gate.
The gas insulated gate field effect transistor is comprised of a semiconductor substrate, a doped source region, a doped drain region, an electrically conducting gate, A gate insulator consisting of a gaseous gate insulating trench, and terminals connected to the gate, the doped source region and the doped drain region. The gaseous gate insulating trench is the sole gate insulator of the gas insulated gate field effect transistor. The doped source region and the doped drain region are formed on the substrate such that the regions have a channel between them. The electrically conducting gate is formed on the substrate on one side of the gaseous gate insulating trench. The gaseous gate insulating trench and the source and drain regions are positioned such that the gate is on one side of the trench and the doped source and the doped drain regions are on the other side of the trench. The terminals are electrically connected to the gate, the doped source region and the doped drain region for providing electrical connection points. In one version of the invention the gate is comprised of metal. In another version of the invention the gate is comprised of polysilicon. When a metallic gate is used, the trench width may be precisely controlled by electroplating the gate to adjust the trench width between the gate and the channel.
A plurality of gas insulated gate field effect transistors on a semiconductor substrate may be interconnected to form an integrated circuit. Each gas insulated gate field effect transistor is fabricated on the same substrate and electrically interconnected with one or more of the other gas insulated gate field effect transistors. Input/output contacts are provided at selected points along the interconnections. Typically, integrated circuits are fabricated by isolating discrete identical circuits on the substrate and cutting the substrate into one or more chips, each chip comprising an isolated discrete identical circuit. The chip is placed within a package. External integrated circuit leads pass from within the package to outside the package. Each lead is wirebonded at its end within the package to a selected input/output contact. Preferably, a selected gas is hermetically sealed within the package at a selected absolute pressure such that the gas permeates each gaseous gate insulating trench. The selected gas may be atmospheric gas reduced to an absolute pressure approximating zero, thereby permeating the gaseous gate insulating trench with a vacuum.
Another aspect of the invention is a method for fabricating a gas insulated gate field effect transistor. A semiconductor substrate is provided. A doped source region and a doped drain region are formed on the substrate such that the regions have a channel between them. A gate pocket is formed on the substrate. A conductive layer is deposited over the surface of the substrate. The layer covers the source region, the drain region and the gate pocket. A trench area on the substrate between the gate pocket and the doped source region and the doped drain region is exposed for forming a trench. The gate pocket is on one side of the trench area. The doped source region and the doped drain region is on the other side of the trench area. A gaseous gate insulating trench is formed through the exposed trench area. A gate terminal, a source terminal and a drain terminal are formed by removing sections of the conductive layer. The conductive layer may be metal. When the gate is comprised of metal, it may be electroplated to precisely reduce the trench width between the gate and the channel.
Another aspect of the invention is a method for fabricating an integrated circuit from gas insulated gate field effect transistors. A plurality of gas insulated gate field effect transistors are fabricated, as described above, on a semiconductor substrate. A plurality of the terminals are electrically interconnected to form desirable circuits. Input/output contacts are formed at selected points along the interconnections. Discrete identical circuits are isolated on the substrate by cutting the substrate into one or more chips. A chip is placed into a package. External integrated circuit leads, passing from within the package to outside the package, are wirebonded at the lead end within the package to selected input/output contacts on the chip. Preferably, the pack
Kang Donghee
Zalecki Gregory T.
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