Electrical connectors – With insulation other than conductor sheath – Insulating body having plural mutually insulated terminals...
Reexamination Certificate
2000-03-27
2001-12-04
Powell, William A. (Department: 1765)
Electrical connectors
With insulation other than conductor sheath
Insulating body having plural mutually insulated terminals...
C216S067000, C216S079000, C252S079100, C438S723000, C438S737000, C438S738000, C438S743000
Reexamination Certificate
active
06325676
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a gas etchant composition and a method for simultaneously etching silicon oxide and polysilicon, and a method for manufacturing semiconductor devices using the same. More particularly, the present invention relates to a gas etchant composition for simultaneously etching silicon oxide and polysilicon during an etch-back process of manufacturing a capacitor for a semiconductor memory device, an etching method thereof, and a method for manufacturing a semiconductor device using the same.
2. Background of the Related Art
Currently, due to widespread usage of computers in information media, memory devices are being developed which provide semiconductor devices with higher memory storage capacity and faster operating speeds. To this end, the current technology in the art is focused on developing and realizing memory devices having a high degree of integration, response speed, and reliability. Conventionally, dynamic random access memory (DRAM) devices, which have a high memory capacity and random open input/output functions, are widely used as semiconductor memory devices.
DRAM devices generally comprise a memory cell having at least one transistor and a capacitor to charge/discharge electrical charges for input/output functioning of information data. Further, DRAM devices conventionally comprise a memory cell region for storing large information data and peripheral circuits for input/out functioning of information data. To obtain a high integration in such DRAM devices comprising a capacitor, it is necessary to decrease the size of the cells, which results in decreased sizes and degree of margins of patterns formed on a semiconductor substrate. Consequently, the aspect ratio of the components which make up the substrate increases.
Conventionally, a stacked-capacitor cell having an electrode comprising polysilicon layers and a dielectric film made from a silicon nitride layer is widely used as a DRAM cell for Mb DRAMs. However, it is difficult to obtain an adequate cell capacitance with the capacitor cell having such a simple stacked structure in highly integrated DRAMs. As such, tantalum oxide layers having a higher dielectric constant are utilized for the dielectric layers in place of silicon nitride layers, or the structure of the stacked-capacitors is changed to increase the effective area of the capacitors.
Generally, to increase the cell capacitance in DRAMs, the storage electrode is heightened to form a stacked-structure. However, in view of the very high integration of semiconductor devices, the size of the cells need to be decreased instead. Thus, in order to increase the cell capacitance, the critical distance between storage electrodes formed on the cells should be decreased or the height of the storage electrode should be increased. However, if the critical distance is decreased, an electrical bridge may form between adjacent storage electrodes, thereby causing a short. If the height of the storage electrode is increased the global step in the devices is also increased, which leads to decreased image margin during the photo-process, thereby causing shorts between the metal wirings in the subsequent processes.
To increase the effective area of the capacitors, a method of forming a rugged shape on the surface of polysilicon layers used for obtaining the storage electrode of capacitors has been suggested. The rugged shape is obtained by an etching process or by manipulating the manufacturing variables which control the process of growing polysilicon layers. A method of manufacturing a capacitor utilizing the above method of forming a rugged shape on the surface of polysilicon layers is described below.
First, a main storage electrode is formed at the surface of a semiconductor substrate, then a hemispherical grained (HSG) polysilicon layer is formed on the whole surface of the storage electrode, followed by an anisotropic etching process, which results in a rugged shaped storage electrode.
The above HSG polysilicon layer is formed on the surface of the main storage electrode by using helium diluted SiH
4
gas under a pressure of 1.0 Torr and at a temperature of 550° C. By utilizing such an HSG polysilicon layer, the cell capacitance can be significantly increased, since the effective area can be increased two to three times over the conventional polysilicon layer not having the rugged shape structure.
As shown by the above, the current technology of increasing the cell capacitance of DRAMs utilizes the method of manufacturing a capacitor having a stacked structure and forming an HSG silicon layer for increasing the effective area. Specifically, for 256 Mb DRAMs, a storage electrode having a one cylinder stacked structure is being widely used. Such a method is disclosed in U.S. Pat. Nos. 5,721,153, 5,817,555 and 5,759,894.
For manufacturing the above stacked-capacitors, a selective etching process for etching a structure of both silicon oxide and polysilicon material must be used. Conventionally, for selectively etching polysilicon in a composite layer having both polysilicon and silicon oxide, a mixed composition of carbon tetrachloride gas and argon gas, a mixed gas of CF
4
and oxygen, CF
3
Cl gas, and a mixed composition of fluoro-carbon type compound and chloride gas are utilized. On the other hand, carbon tetrafluoride gas, C
2
F
4
gas, and CHF
3
gas are utilized for selectively etching silicon oxide.
However, distinct homogeneous layers of silicon oxide or polysilicon can be etched simultaneously. For example, U.S. Pat. No. 5,228,950 discloses a method of removing residues from oxide and silicon materials by using an etchant gas comprising NF
3
as a main constituent.
Accordingly, in the conventional etching process, an etchant and etching equipment are selected based upon the type of material to be etched, such as polysilicon, oxide or metals. Preferably, for selectively etching layers near or adjacent to layers not to be etched, an etchant having a high selectivity for the layer to be etched is selected. In this respect, gate electrodes and bit-lines, which conventionally comprise polysilicon, are etched by utilizing polysilicon etching equipment, while silicon oxide etching equipment is used for etching insulating layers of hot temperature oxide (HTO) and BPSG, which conventionally comprise silicon oxide.
However, recently, as semiconductor devices become more highly integrated, the conventional etching process described above is becoming inadequate for more complicated processes. Particularly, in the process of manufacturing semiconductor devices, a composite layer comprised of a number of different materials such as polysilicon and silicon oxide is currently used in various components as opposed to a conventional single layer structure. Accordingly, the semiconductor manufacturing industry has been attempting to find a method of effectively etching composite layers comprising both polysilicon and silicon oxide.
FIGS. 1A
to
1
J are sectional views illustrating a manufacturing process of a conventional semiconductor device comprising a capacitor having a cylindrical shape.
Referring to
FIG. 1A
, on a semiconductor substrate
70
made from a semiconductor material such as silicon, a field oxide layer
75
for defining the active regions of various devices on the substrate
70
is formed by a local oxidation of silicon (LOCUS) method. On the active region defined by the field oxide layer
75
, a gate oxide layer
80
is formed by thermal oxidation.
A first polysilicon layer and subsequently a first insulating layer made from silicon oxide are then formed on the surface of the substrate
70
. The first polysilicon layer and first insulating layer are then etched to obtain gate electrodes
95
each having a polysilicon pattern
85
and an insulating layer pattern
90
on its respective gate oxide layer
80
or field oxide layer
75
. Thereafter, utilizing the gate electrode
95
as an ion implantation mask, a low concentration impurity region on the semiconductor substrate
70
Jung Kwang Jin
Park Il Jeong
Francos, PLLC Volentine
Powell William A.
Samsung Electronics Co,. Ltd.
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