Adhesive bonding and miscellaneous chemical manufacture – Differential fluid etching apparatus – With microwave gas energizing means
Reexamination Certificate
1999-09-23
2002-09-17
Utech, Benjamin L. (Department: 1765)
Adhesive bonding and miscellaneous chemical manufacture
Differential fluid etching apparatus
With microwave gas energizing means
C438S706000
Reexamination Certificate
active
06451157
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to reaction chambers used for processing semiconductor substrates, such as integrated circuit wafers, and specifically to improvements in the gas distribution system used in these reaction chambers.
BACKGROUND OF THE INVENTION
Semiconductor processing includes deposition processes such as chemical vapor deposition (CVD) of metal, dielectric and semiconducting materials, etching of such layers, ashing of photoresist masking layers, etc. In the case of etching, plasma etching is conventionally used to etch metal, dielectric and semiconducting materials. A parallel plate plasma reactor typically includes a gas chamber including one or more baffles, a showerhead electrode through which etching gas passes, a pedestal supporting the silicon wafer on a bottom electrode, an RF power source, and a gas injection source for supplying gas to the gas chamber. Gas is ionized by the electrode to form plasma and the plasma etches the wafer supported below the showerhead electrode.
Showerhead electrodes for plasma processing of semiconductor substrates are disclosed in commonly assigned U.S. Pat. Nos. 5,074,456; 5,472,565; 5,534,751; and 5,569,356. Other showerhead electrode gas distribution systems are disclosed in U.S. Pat. Nos. 4,209,357; 4,263,088; 4,270,999; 4,297,162; 4,534,816; 4,579,618; 4,590,042; 4,593,540; 4,612,077; 4,780,169; 4,854,263; 5,006,220; 5,134,965; 5,494,713; 5,529,657; 5,593,540; 5,595,627; 5,614,055; 5,716,485; 5,746,875 and 5,888,907. Of these, the '816 patent discloses a single wafer plasma etching chamber wherein the upper electrode assembly includes an electrode of stainless steel, aluminum or copper and a baffle of conductive material or sintered graphite.
A common requirement in integrated circuit fabrication is the etching of openings such as contacts and vias in dielectric materials. The dielectric materials include doped silicon oxide such as fluorinated silicon oxide (FSG), undoped silicon oxide such as silicon dioxide, silicate glasses such as boron phosphate silicate glass (BPSG) and phosphate silicate glass (PSG), doped or undoped thermally grown silicon oxide, doped or undoped TEOS deposited silicon oxide, etc. The dielectric dopants include boron, phosphorus and/or arsenic. The dielectric can overlie a conductive or semiconductive layer such as polycrystalline silicon, metals such as aluminum, copper, titanium, tungsten, molybdenum or alloys thereof, nitrides such as titanium nitride, metal silicides such as titanium silicide, cobalt silicide, tungsten silicide, molybdenum silicide, etc. A plasma etching technique, wherein a parallel plate plasma reactor is used for etching openings in silicon oxide, is disclosed in U.S. Pat. No. 5,013,398.
U.S. Pat. No. 5,736,457 describes single and dual “damascene” metallization processes. In the “single damascene” approach, vias and conductors are formed in separate steps wherein a metallization pattern for either conductors or vias is etched into a dielectric layer, a metal layer is filled into the etched grooves or via holes in the dielectric layer, and the excess metal is removed by chemical mechanical planarization (CMP) or by an etch back process. In the “dual damascene” approach, the metallization patterns for the vias and conductors are etched in a dielectric layer and the etched grooves and via openings are filled with metal in a single metal filling and excess metal removal process.
There is a need in the art of semiconductor processing for improved reactor designs wherein contamination due to metals and/or particles is reduced and the time between wet cleans is increased to improved wafer production efficiency. Although efforts have been made to improve reactor designs, any improvements which achieve the abovementioned goals are highly desirable, particularly in the field of oxide etching.
SUMMARY OF THE INVENTION
The invention provides a baffle plate which reduces particle and/or metal contamination during processing of a semiconductor substrate. The baffle plate is adapted to fit within the baffle chamber of a showerhead gas distribution system 5 such that a silicon containing surface of the baffle plate is adjacent to and facing the showerhead. The baffle plate can consist essentially of silicon or a silicon compound such as silicon carbide. A preferred baffle plate material is silicon carbide having a purity of at least 99.999% and/or a porosity of 10 to 30%. The silicon carbide baffle plate can be made entirely of non-sintered silicon carbide, sintered silicon carbide, bulk CVD silicon carbide, sintered silicon carbide with a CVD coating of silicon carbide, graphite coated with silicon carbide, reaction synthesized silicon carbide, or combination thereof.
According to one aspect of the invention, the silicon containing baffle plate can be used as a drop-in replacement for an aluminum baffle plate. When mounted in a baffle chamber, the silicon containing baffle plate can include openings therethrough for passage of process gas, wherein the openings are offset from openings in the showerhead. In order to provide a plenum between the silicon containing baffle plate and an adjacent aluminum baffle plate, the silicon containing baffle plate can include a rim extending around the periphery thereof.
In use, the silicon containing baffle plate can be part of a gas distribution system of a plasma processing chamber wherein the gas distribution system includes a showerhead electrode and the silicon containing baffle plate is mounted in a baffle chamber such that the silicon containing surface faces the showerhead electrode and an opposite side of the silicon containing baffle plate faces an aluminum baffle plate. In such an arrangement, the silicon containing baffle plate is effective to reduce metal contamination by at least an order of magnitude during plasma processing of a semiconductor substrate in the chamber compared to the metal contamination produced under the same processing conditions but using an aluminum baffle plate in place of the silicon containing baffle plate.
The invention also provides a method of reducing particle and/or metal contamination during processing of a substrate in a reaction chamber wherein a gas distribution system includes a showerhead, a baffle chamber through which process gas passes to the showerhead, and a silicon containing baffle plate located in the baffle chamber, the method comprising supplying a semiconductor substrate to the reaction chamber, supplying process gas into the baffle chamber, the process gas passing through the silicon containing baffle plate into a space between the silicon containing baffle plate and the showerhead followed by passing through the showerhead and into an interior of the reaction chamber, and processing the semiconductor substrate with the process gas passing through the showerhead.
According to a preferred method, the showerhead is a showerhead electrode which energizes the process gas passing therethrough into a plasma state. The method can comprise etching a layer on the semiconductor substrate by supplying RF power to the showerhead electrode such that the process gas forms a plasma in contact with an exposed surface of the semiconductor substrate. For example, the semiconductor substrate can comprise a silicon or gallium arsenide wafer and the method can include dry etching a dielectric, semiconductive or conductive layer of material on the wafer. Alternatively, the method can include depositing a layer of material on the semiconductor substrate. In the case where the showerhead comprises a showerhead electrode attached to a temperature-controlled member, the method can include withdrawing heat from the showerhead electrode by passing coolant through the temperature-controlled member. In the case of etching, openings can be etched through exposed portions of a dielectric layer of the substrate to an electrically conductive or semiconductive layer of the substrate. For example, the etching step can be carried out as part of a process of manufacturing a damascene structure. Fur
Burns Doane , Swecker, Mathis LLP
Lam Research Corporation
Utech Benjamin L.
Vinh Lan
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