Garbage collection barrier with direct user mode traps

Details Garbage collection barrier with direct user mode traps Garbage collection barrier with direct user mode traps

2009-11-25

2011-10-25

Elmore, Reba I. (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S200000, C711S206000

Reexamination Certificate

active

08046544

ABSTRACT:
A computer system includes a processor; and a memory coupled to the processor, configured to provide the processor with a plurality of instructions including a set of garbage collection instructions configured to perform one or more garbage collection barrier operations and a subsequent instruction that immediately follows the garbage collection instruction; wherein the processor is configured to execute the set of garbage collection instructions, including by: evaluating a memory reference to determine a condition associated with the set of garbage collection instructions; and in the event that the condition is met, while maintaining the same privilege level, saving information that is based at least in part on the current value of a program counter, and setting the program counter to correspond to a target location that is other than the location of the subsequent instruction.

REFERENCES:
patent: 5845298 (1998-12-01), O'Connor et al.
patent: 6226653 (2001-05-01), Alpern et al.
patent: 6470361 (2002-10-01), Alpern et al.
patent: 6510440 (2003-01-01), Alpern et al.

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