Gapfill improvement with low etch rate dielectric liners

Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching

Reexamination Certificate

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C257SE21546, C257SE21396

Reexamination Certificate

active

07910491

ABSTRACT:
A method of filling a trench is described and includes depositing a dielectric liner with a high ratio of silicon oxide to dielectric liner etch rate in fluorine-containing etch chemistries. Silicon oxide is deposited within the trench and etched to reopen or widen a gap near the top of the trench. The dielectric liner protects the underlying substrate during the etch process so the gap can be made wider. Silicon oxide is deposited within the trench again to substantially fill the trench.

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PCT International Search Report and Written Opinion mailed Apr. 30, 2010, International Application No. PCT/US2009/058832, 13 pages.

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