Gap filling process in integrated circuits using low...

Details Gap filling process in integrated circuits using low... Gap filling process in integrated circuits using low...

1999-07-12

2001-03-27

Bowers, Charles (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S633000, C438S627000, C438S628000, C438S637000

Reexamination Certificate

active

06207554

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically it relates to structures for reducing capacitance between closely spaced interconnection lines of integrated circuits. In particular, it pertains to structures and methods for improving adhesion and preventing micro cracks in low dielectric constant materials when used in conjunction with conventional dielectric materials as intermetal dielectrics (IMD).
(2) Description of Prior Art
Integrated circuits and the progress made in Silicon Technology has continued to shrink the size of devices. This has led to closer and closer spacing of interconnection lines. As spacing becomes closer, the capacitance between adjacent lines has increased, as device geometries shrink and circuit densities increase. The capacitance between lines is directly related to both the distance between the lines and dielectric constant of the material in between the lines. Hence, a low dielectric material between the closely spaced interconnect lines is beneficial in reducing the capacitance.
In 0.25 micron, or below (e.g., 0.18, 0.13 um), technology the performance is limited by the interconnect line delay, with line-to-line capacitance being greatly affected by RC delay of the lines, as line width and line space becomes less than about 0.3 microns. Therefore, the introduction of low dielectric materials between the closely spaced interconnect, transmission lines can greatly enhance the integrated circuit performance in terms of speed, by lowering the RC time constants.
U.S. Pat. No. 5,818,111 entitled “Low Capacitance Interconnect Structures in Integrated Circuits Using a Stack of Low Dielectric Materials” granted Oct. 6, 1998 to Jeng and Taylor describes a method and structure for integrating hydrogen silsesqui-oxane (HSQ) and other low dielectric materials, which have undesirable properties, into integrated circuit structures and processes. A stabilizing layer is inserted between layers of low dielectric constant films. A layer of low dielectric constant HSQ is spun over and in between metal interconnect lines with a thin layer of silicon dioxide used as a stabilizing layer on top. Alternating layers of HSQ and thin silicon dioxide are fabricated together with multilevel metal structures. Finally, a thick silicon dioxide layer for planarization is placed on top of the multi-level metal layer structures.
U.S. Pat. No. 5,759,906 entitled “Planarization Method for Intermetal Dielectrics Between Multilevel Interconnections on Integrated Circuits” granted Jun. 2, 1998 to Lou describes a method for making a planar intermetal dielectric layer (IMD) for multilevel electrical interconnections on ULSI circuits. The method involves forming metal lines on which is deposited a conformal PECVD oxide. A multilayer of spin-on glass (SOG), composed of at least four layers, is deposited and baked at elevated temperatures and long times after each layer to minimize the poisoned via problem. After depositing a silicon dioxide layer on the SOG, the layer is partially chemical/mechanically polished to provide the desired, more global planar, IMD. The method can be repeated for multilevel metal lines.
U.S. Pat. No. 5,385,866 entitled “Polish Planarizing Using Oxidized Boron Nitride as a Polish Stop” granted Jan. 31, 1995 to Bartush shows a method of polishing of a non-planar surface layer on a semiconductor substrate using an oxidized boron nitride polishing stop layer. The oxidized boron nitride polish stop layer is selectively polished relative to the non-planar surface layer. The oxidized boron nitride acts as a polishing stop layer for the process over an FET gate structure.
U.S. Pat. No. 5,821,621 entitled “Low Capacitance Interconnect Structure for Integrated Circuits” granted Oct. 13, 1998 to Jeng shows a method for integrating polymer and other low dielectric constant materials, which may have undesirable physical properties, into integrated circuits structures and processes, especially those requiring multiple levels of interconnect lines. It combines the use of silicon dioxide with low dielectric constant materials. The low dielectric constant materials are spun-on and defined by photolithography to be only in the critical areas between interconnect lines. After planarization, the process steps can be repeated for multiple interconnect layers.
SUMMARY OF THE INVENTION
It is the general object of the present invention to provide an improved method of fabricating semiconductor integrated circuit devices, specifically by describing an improved process of fabricating multilevel metal structures using low dielectric constant materials. Furthermore, the present invention relates to an improved method for fabricating stable and planar intermetal dielectric materials, using low dielectric constant materials.
The method by the first embodiment of this invention, uses a stabilizing adhesion layer between the bottom, low dielectric constant layer and the top dielectric layer. The advantages of the stabilizing adhesion layer are: (i) improved adhesion and stability of the low dielectric layer and the top dielectric oxide (ii) over all layer thickness of the dielectric layers can be reduced, hence lowing the parasitic capacitance of these layers.
In the second embodiment of the present invention, the method uses a multi-layered “hard mask” on metal interconnect lines with an underlying silicon oxynitride DARC, dielectric anti-reflective coating. The term hard mask refers to these layers that exhibit resistance to being chemical-mechanical polished (CMP) back in the planarization process. A double coating scheme of low dielectric constant insulators are used in this application of the invention. Several advantages are achieved by this method: (i) improved global planarization with low dielectric constant material used in conjunction with hard mask (ii) adhesion and stabilizing material used between low dielectric material and oxide dielectric (iii) double coat of low dielectric material for whole interlevel metal dielectric (IMD) stack.
Still another object of this invention, is the third embodiment of the present invention, a multi-layered hard mask stack over the interconnect metal lines with silicon oxynitride DARC, dielectric anti-reflective coating, is used, and in addition, an adhesion and stabilization layer is used between the low dielectric material and the top dielectric layer. In this application of the invention, several advantages are achieved: (i) improved global planarization (ii) reduction of outgassing and via poisoning (iii) easy integration of low dielectric constant material.
The present invention starts with conventional processing of the semiconductor substrate and continues with conventional processing up to the fabrication of the first level of metal interconnect lines. A detailed description of the aforementioned conventional processing is found in the section titled, “DESCRIPTION OF THE PREFERRED EMBODIMENTS”.
Integrated circuits and the progress made in Silicon Technology has continued to shrink the size of devices. This has led to closer and closer spacing of interconnection lines. As spacing becomes closer, the capacitance between adjacent lines has increased, as device geometries shrink and circuit densities increase. The capacitance between lines is directly related to both the distance between the lines and dielectric constant of the material in between the lines. Hence, a low dielectric material between the closely spaced interconnect lines is beneficial in reducing the capacitance.
In quarter micron technology and below, the performance is limited by the interconnect line delay, with line-to-line capacitance being greatly affected by RC delay of the lines, as line width and line space becomes less than about 0.3 microns. Therefore, the introduction of low dielectric materials between the closely spaced interconnect, transmission lines can greatly enhance the integrated circuit performance in terms of speed, by lowering t

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