Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-02-22
2001-11-20
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S687000
Reexamination Certificate
active
06319831
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to the formation of high aspect ratio metal and vias by electrochemical deposition.
(2) Background of the Invention and Description of Prior Art
Integrated circuits are manufactured by forming discrete semiconductor devices in the surface of silicon wafers. A multi-level metallurgical interconnection network is then formed over the devices, contacting their active elements, and wiring them together to create the desired circuits. The wiring layers are formed by depositing an insulating layer over the discrete devices, patterning and etching contact openings into this layer, and then depositing conductive material into the openings. A conductive layer is applied over the insulating layer and patterned to form wiring interconnections between the device contacts, thereby creating a first level of basic circuitry. The circuits are then further interconnected by utilizing additional wiring levels laid out over additional insulating layers with conductive via pass throughs. Depending upon the complexity of the overall integrated circuit, several levels of wiring interconnections are used.
A method for forming the interconnection layer is the damascene process, whereby openings and trenches, comprising an image of the interconnection pattern are formed in an insulative layer. A metal layer is then deposited into the openings and over the insulative layer. Finally, the metal is polished back to the insulative layer leaving the metal pattern inlaid within the insulative layer. Polishing back of the metal layer is accomplished by CMP (chemical mechanical polishing), a relatively old process which has found new application in planarization of insulative layers and more recently in the damascene process. In a single damascene process a metal line pattern is generated which connects to subjacent vias or contacts. In a dual damascene process, both vias and contacts and an interconnection stripe pattern are formed by a single metal deposition and CMP. A description of both single and dual damascene processes may be found in Chang, C. Y. and Sze, S. M., “ULSI Technology” McGraw-Hill, New York, (1996), p444-445 and in El-Kareh, B., “Fundamentals of Semiconductor Processing Technologies”, Kluwer, Boston(1995), p563-4.
Deposition of the metal layer can be by PVD (physical vapor deposition) methods such as sputtering or vacuum evaporation, by CVD (chemical vapor deposition), or by ECD (electrochemical deposition). The ECD method involves placing the wafer into an electrolyte bath and electro plating a metal layer onto the wafer surface by applying of an electric field between the wafer and the electrolyte. The ECD method has been found to be particularly desirable for the deposition of copper.
Chen, U.S. Pat. No. 5,723,387 shows a method and apparatus for the preparation of a copper interconnection metallurgy using eletroplating or electroless plating techniques. The copper is deposited onto a TiW barrier layer which itself is deposited by electroless plating. The disclosed apparatus includes a CMP station for polishing the copper plate after deposition. Sandhu, et.al., U.S. Pat. No. 5,662,788 shows a process for selective electrochemical deposition of a metal layer using an alternating voltage superimposed on a dc potential and a patterned layer having a higher surface potential than a subjacent non-patterned layer. Although the metal deposits on both the patterned layer and the exposed subjacent layer during the first half of the voltage cycle, it is selectively removed from the subjacent layer during the second half of the cycle, leaving the metal deposited only on the patterned layer. Gilton, et.al., U.S. Pat. No. 5,151,168 shows an ECD process wherein current densities of less than 1 milliampere/cm
2
are used to deposit copper onto a barrier layer to fill contact and via openings. Such low current densities, although producing good quality copper deposits would also be expected to have a very low throughput.
In the electroplating process, brighteners and levelers are added to the electrolyte to improve the quality and conformality of the deposited metal layer. Levelers are additives which adsorb onto high field regions of the substrate in the plating bath. Such regions occur at protrusions and sharp outside corners. The levelers adsorb on these regions and thereby inhibit the growth rate of the plated film in these regions, producing a rounding or smoothing over of the corners or protrusions. Brighteners are additives which adsorb onto regions of low electric field and participate in the charge transfer mechanism of the electrochemical deposition process. Brighteners, affect crystalline quality by refining grain size which is critical to control sheet resistance and electromigration tolerance.
Brighteners are consumed by the electrochemical process and must therefore be replenished at the growth front during the ECD. In conventional plating processes, brighteners are replenished at the reaction front from the bulk of the electrolyte, by normal diffusion assisted by mechanical agitation of the plating bath. However, in the presence of high aspect ratio contact/via openings and trenches typically found in current high density integrated circuits, conventional agitation of the electrolyte becomes inadequate for timely replenishment of the depleted brighteners at the bases of the openings and trenches. Replenishment of additives must then rely on diffusion alone, requiring the reduction of deposition current density and thereby the process throughput. The film quality and throughput of the currently used single step ECD processes are therefore limited by the mass transfer of additives to the deposition front. An Inadequate supply of these additives at the deposition front results in poor gap filling as well as reduced mechanical and electrical quality of the electrodeposited metal layer.
It is therefore desirable to have a process which would provide good gap filling of high aspect ratio openings and also provide a high throughput for metal layers deposited onto damascene type structures.
SUMMARY OF THE INVENTION
Accordingly, it is an object of this invention to provide a method for improving the metal quality and filling by electrochemical deposition, of damascene structures having high aspect ratio openings and trenches.
It is another object of this invention to provide an improved method of increasing the throughput of an electrochemical deposition process for forming metal layers on damascene structures.
These objects are accomplished by performing the an initial step of the electrochemical deposition at a low current density whereby the deposition is highly conformal and the deposition rate is sufficiently low so that brightener depletion at the base of high aspect ratio features is kept at a minimum. During this initial deposition stage, a large portion of the high aspect ratio features are filled along the sidewalls and the bottom filling is high. Following the low current density step, the deposition process is stopped by removing the applied potential and a dwell period is entered wherein brightener additive molecules are permitted to diffuse into the lower regions of the high aspect ratio openings and/or trenches, replenishing these regions. A final deposition period is then begun at a high current density wherein the high aspect ratio openings and/or trenches are filled and the remainder of the top surface metal is deposited.
The dwell period between the low current and the high current electroplating steps, although benefitting local deposit uniformity, comes at a price which must be considered. One of the benefits of having reduced concentration of brighteners and levelers at the deposition front due to is that the growth rate is enhanced in this region. This is because the presence of leveler chemicals reduces the growth rate. By permitting the leveler concentration to deplete in the openings, the copper growth rate tends to
Tsai Ming-Hsing
Tsai Wen-Jye
Ackerman Stephen B.
Lee Calvin
Saile George O.
Smith Matthew
Taiwan Semiconductor Manufacturing Company
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