Gallium arsenide planar tunnel diode method

Details Gallium arsenide planar tunnel diode method Gallium arsenide planar tunnel diode method

1987-06-18

1988-05-24

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156657, 1566591, 156662, 437 72, 437192, 437202, 437235, B44C 122, H01L 2158, H01L 2160, C03C 1500

Patent

active

047463988

ABSTRACT:
A gallium arsenide tunnel diode is fabricated using planar techniques from a wafer of gallium arsenide that has been heavily doped to form a P region. Tin is plated onto an exposed section of a surface of the wafer and then melted to cause individual tin atoms to diffuse only a few atomic layers into the wafer, creating a heavily doped N region. Metal contact layers are then formed over the tin and on the opposite surface of the wafer. An oxidation inhibitor is used during the plating and a scavenging agent is used during the melting to insure intimate contact between the tin and the wafer.

REFERENCES:
patent: 4179533 (1979-12-01), Christou et al.
patent: 4187599 (1980-02-01), Flowers et al.
patent: 4307131 (1981-12-01), Moutou et al.

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