Gain enhanced split drive buffer

Details Gain enhanced split drive buffer Gain enhanced split drive buffer

1997-08-22

2000-02-15

Tokar, Michael

Electronic digital logic circuitry

Interface

Current driving

326 95, H03K 190175

Patent

active

060257385

ABSTRACT:
A system and method for increasing the gain per stage and signal edge transition speed, as well as the edge phase accuracy of an input signal. In an exemplary embodiment, a distributed clock signal is produced by an enhanced clock buffer circuit which includes additional weighted static gain chains connected within the buffer circuit. The buffer circuit retains the benefits of the split-drive, dual output transistor configuration, and also substantially improves circuit gain per delay gate by connecting the weighted static gain chains between pulse generators and output transistors of the buffer circuit. The gain chains are designed to rapidly propagate the edge that fires their respective output transistors but slowly propagate the edge that turns the output transistor off, by reducing the devices that propagate the shut-off transition. N-type and p-type devices within the buffer circuit are arranged and sized to promote the gain characteristic of the split drive buffer circuit.

REFERENCES:
patent: 4833349 (1989-05-01), Liu et al.
patent: 5128560 (1992-07-01), Chern et al.
patent: 5598119 (1997-01-01), Thayer et al.
patent: 5604454 (1997-02-01), Maguire et al.
patent: 5610548 (1997-03-01), Masleid

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