Gain controller using switched capacitors

Details Gain controller using switched capacitors Gain controller using switched capacitors

2002-01-11

2003-05-13

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific input to output function

By integrating

C327S341000

Reexamination Certificate

active

06563364

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to gain controlling circuitry, and more particularly, to a gain controller for digitally controlling the gain of an input signal using switched capacitors.
2. Description of the Related Art
FIG. 1
is a block diagram of a conventional gain controller for controlling the gain of an input signal using switched capacitors. The gain controller of
FIG. 1
includes feedback capacitors C
F1
and C
F2
, an operational amplifier
10
, input capacitors C
I1
and C
I2
, and MOS transistors MN
1
through MN
7
which operate as switches.
FIG. 2
shows waveforms of first and second control clock signals Q
1
and Q
2
for controlling the opening and closing of the MOS transistors MN
1
through MN
7
shown in
FIG. 1
, which operate as the switches. The clock signals Q
1
and Q
2
of
FIG. 2
are applied to MOS transistors MN
1
through MN
7
as shown in FIG.
1
. Specifically, Q
1
is used to control MOS transistors MN
3
through MN
7
, and Q
2
is used to control MN
1
and MN
2
. It is noted that the falling edge of the first control clock signal Q
1
does not overlap the rising edge of the second control clock signal Q
2
. This is to prevent the MOS transistors MN
1
and MN
2
and the MOS transistors MN
3
through MN
7
from being simultaneously turned on.
The gain controller shown in
FIG. 1
operates in two modes. Namely, the gain controller operates in a sampling mode when the first control clock signal Q
1
is at a logic “high” level and operates in an amplifying mode when the second control clock signal Q
2
is at the logic “high” level.
Charge amounts Q
I1
and Q
I2
charged to the input capacitors C
I1
and C
I2
, respectively, in the sampling mode are equal to the sums Q
f1
and Q
f2
of charge amounts charged to the input capacitors C
I1
and C
I2
and the feedback capacitors C
F1
and C
F2
, respectively, in the amplifying mode. When the capacitance of the input capacitors C
I1
and C
I2
is C
I
and the capacitance of the feedback capacitors C
F1
and C
F2
is C
F
, the following relationship is established between the difference V
INT
−V
INC
between input voltages V
INT
and V
INC
and the difference V
OUTT
−V
OUTC
between output voltages V
OUTT
and V
OUTC
.
V
OUTT
-
V
OUTC
=
C
I
C
F
⁢
(
V
INT
-
V
INC
)
.
(
1
)
A feedback factor is 1/&bgr; in the amplifying mode. Here, &bgr; is a feedback gain value, which is represented as follows.
β
=
C
F
C
I
+
C
F
(
2
)
As the above-mentioned feedback factor 1/&bgr; increases, the operating speed of the gain controller shown in
FIG. 1
is reduced. Therefore, in order to increase the operating speed of the gain controller, the value of P defined by Equation 2 must be increased.
It is assumed that the MOS transistors MN
1
and MN
3
and the input capacitor C
I1
shown in
FIG. 1
constitute a cell. A plurality of cells are connected to the negative input terminal of the operational amplifier
10
in parallel. Also, it is assumed that the MOS transistors MN
2
and MN
4
and the input capacitor C
I2
constitute another cell. A plurality of cells are connected to the positive input terminal of the operational amplifier
10
in parallel. In order to select desired cells among the cells connected in parallel, an externally generated digital gain control signal is used. Accordingly, the value of the gain C
I
/C
F
shown in Equation 1 can be changed.
In the conventional gain controller, the digital gain control signal is used in order to change the value of C
I
/C
F
. Only one cell is selected. The input capacitance of the capacitor included in the selected cell is previously set so as to obtain a desired value of C
I
/C
F
. Namely, when the gain C
I
/C
F
of the difference V
INT
−V
INC
is to be controlled as a C
I
/C
F
in the conventional gain controller, corresponding two cells, which include the capacitor having the capacitance a*C
F
′ (C
F
′ is the capacitance of C
F
), are to be selected in response to the digital gain control signal among the plurality of cells connected to the positive and negative input terminals of the operational amplifier
10
in parallel.
For example, it is assumed that the capacitance of the feedback capacitor CF is set to be C
O
and that first through fourth cells are connected to the negative input terminal of the operational amplifier
10
in parallel. Also, it is assumed that fifth through eighth cells are connected to the positive input terminal of the operational amplifier
10
in parallel and that the capacitor included in the first cell and the capacitor included in the fifth cell have the capacitance C
O
. Also, it is assumed that the capacitor included in the second cell and the capacitor included in the sixth cell have capacitance 2C
O
and that the capacitor included in the third cell and the capacitor included in the seventh cell have capacitance 4C
O
. Also, it is assumed that the capacitor included in the fourth cell and the capacitor included in the eighth cell have capacitance 8C
O
and that the gain of the difference is controlled by the digital gain control signal of two bits. In the conventional gain controller, in order to control the gain of the difference to be ‘1’, a digital gain control signal ‘00’ is received and the capacitors included in the first and fifth cells are selected. Also, in the conventional gain controller, in order to control the gain of the difference to be ‘2’, a digital gain control signal ‘01’ is received and the capacitors included in the second and sixth cell are selected. In the conventional gain controller, in order to control the gain to be ‘4’, a digital gain control signal ‘10’ is received and the capacitors included in the third and seventh cells are selected. Also, in the conventional gain controller, in order to control the gain to be ‘8’, a digital gain control signal ‘11’ is received and the capacitors included in the fourth and eighth cells are selected. In this case, the feedback gain p of the gain controller shown in
FIG. 1
becomes {fraction (1/16)}. This is because C
F
is C
O
and C
I
is 15C
O
in Equation 2. Also, in this case, the feedback factor is ‘16’.
FIG. 3
is a bode plot for describing the operation of the gain controller shown in FIG.
1
. The horizontal axis denotes frequency and the vertical axis denotes open loop gain represented by dB. The operational amplifier
10
shown in
FIG. 1
has the frequency characteristic
20
as shown in FIG.
3
. The operation frequency of the gain controller shown in
FIG. 1
is f
−3 dB
, which is a point where the feedback factor 1/&bgr; (illustrated by reference numeral
22
) of the gain controller shown in
FIG. 1
crosses the frequency characteristic
20
of the gain controller. Here, the operation frequency f
−3 dB
increases as the feedback factor 1/&bgr; decreases. Also, as the operation frequency f
−dB
increases, the operating speed of the gain controller increases. However, in the conventional gain controller shown in
FIG. 1
, the feedback factor is ‘16’. Accordingly, the operating speed is not as fast.
In particular, when the gain must be controlled to be precise over a wide range, only two corresponding cells must be selected and the capacitances of the capacitors included in the selected cells must be increased. Therefore, the entire sampling capacitance, for example, C
O
+2C
O
+4C
O
+8C
O
increases. Accordingly, the feedback gain is exponentially reduced. As the feedback gain is exponentially reduced, the feedback factor increases. The operating speed is significantly reduced as the feedback factor increases as shown in FIG.
3
.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a gain controller using switched capacitors, capable of very quickly controlling the gain of an input signal with low power consumption.
To achieve the above object, there is provided a gain controller which is operable in a sampling mode or an amplifying mode and which controls the gain of an analog input signal. The gain controller

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